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• Desktop and Android App Status

  BunneyDude • 08/21/2014 at 04:41 • 0 comments

  I never got around to cleaning up my initial SSMU app code and posting it to my GitHub. Shortly after I started working on a app that could render shapes requested by an Intel Galileo board over WiFi. It started with the same base code as the original SSMU app and was able to reuse the same communication protocol as well. 

  Now I'll be able to fully merge the changes from the original SSMU and the WiFiScreen code since the goal is to have both wired and wireless communication. As a bonus, since my previous code was developed for the Intel Galileo board, it will be easy to port the relevant portions to a BeagleBone Black or Raspberry Pi. This way the smaller single-board computer can act as a hub and translate the nRF24L01+ payloads to WiFi ones. 

  Leveraging these common devices means that I don't need to increase the SSMU BOM just to include a WiFi radio and can instead use the much cheaper (~$1) nRF module.

• Updated Bode plot circuit

  BunneyDude • 08/20/2014 at 06:31 • 0 comments

  After skimming through some data sheets I noticed the initial voltage buffer wasn't very useful as-is. The MAX44252 only has 2pF input capacitance so to balance out the loading of the DUT's capacitance I added C2 to compensate. For now it's a placeholder until I run more calculations to see what the feasible range of capacitances the DUT will have.

  I've also replaced the discrete comparator for phase measurement with an internal one on the STM32L100RBT6. Originally I wanted to keep the phase output separate so I could easily hook up other microcontrollers and evaluate them as an alternative to the STM32.

  The power rail for U1 isn't finalized since I'm determining to what extent I should protect the SSMU from the DUT area. The idea is to teach someone filters and such using this project but if they build something with too high a Q factor it could release some magic smoke on the board.

• Selecting the op amps

  BunneyDude • 08/19/2014 at 07:15 • 0 comments

  The op amps form the most important analog part of the SSMU - the magnitude and phase measurements of a sine wave (the Bode plot circuits). They also amplify the DAC output for the device/circuit under test.
  

  I first determined what kind of slew rate I would need. While I planned for a maximum output voltage of 15V, I initially relaxed this down to 9V to make sure I wasn't filtering out any op amps with compelling specs or prices. There are two main frequencies of interest - 20kHz and 100kHz. The first is the required max for audible sound and the second is the cutoff I picked so a filter at 100kHz would do a decent job of attenuating the DAC switching frequency. This calls for a slew rate of 1.88-9.42V/us for 15V max or 1.26-6.28V/us for 9V max.
  

  Next I looked at the errors introduced by input offset voltage and input bias current. With a 12bit ADC at 3.3V, 1LSB = 0.806mV. There are about 4 op amps cascaded in the Bode plot circuit (1 with up to 5V/V gain).
  

  Finally, I needed a supply rail up to 9-15V at a reasonable price. Based on these points I've currently picked the MAX44252. It comes in a quad package for $2.64 and while it doesn't quite have the 15V slew rate for 100kHz (8V/us) it does have a pretty good input offset voltage (3-6uV) and input bias current (200pA).

• Summary of previous work

  BunneyDude • 08/16/2014 at 06:27 • 0 comments

  I started kicking around the idea behind the SSMU roughly a year ago. In February threw a MSP430 and Intel Galileo board together for a simple proof of concept. At the time I was focused on getting the software on the Galileo and desktop working. 

  I was pretty happy with the result - the Java program was able to send a ngspice file to Galileo, request a simulation, trigger a series of ADC conversion from the MSP430, and plot the results side-by-side.

  After helping teach an introduction to electronics workshop for the public a few months later, I decided to revisit the SSMU project. I relaxed some of my initial constraints (e.g. through hole components) and focused on integrating more features.

  Currently the analog side of the schematic is mostly planned out. I've made initial choices for the current source and current sense blocks and will be finalizing the Bode blocks next.

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