Only 4 days since I've posted a log? Being on vacation messes with your sense of time if you stay home... Anyhow, I've been working on board layout for about a day and a half and I'm about half way done with the easy stuff, I think.

If you open the pic up to a larger form You'll see what I'll be doing next. Now, this layout is similar to that of my previous iterations, though I didn't realize how much difficulty I was forcing myself to go through to maintain this form factor.

Right now I have the traces for 2 displays going under the analog inputs. That is also about half of the routing for the displays too. For simplicities sake I'm going to swap the nomenclature of the displays; this alone is overcoming personal stubbornness and a little OCD. Basically what it'll end up looking like is just having the displays rotated to CW to the left edge and the analog inputs rotated CCW to the bottom edge. The JTAG header will probably move down further  from what I can see though.

Either way, the routing for the software SPI will be a tad difficult, but that's 3 lines instead of 12. Display 1 will become 3, 2 will be 1, and 3 will be 2. Memory layout with forced serial termination, which may not be needed for speed though should help with noise suppression, was a lot simpler and I didn't bother trace length matching. I can go on over the changes, but I'm back to work tomorrow and there are few changes from the last update I posted.

Schematic capture will be up on github soon though I'm not recording sub-versioning due to changes or what not that come up with the layout. Once I finish this layout, I'll post more details.

Last tid bit. I don't have code running, but due to problems encountered with existing hardware, it wouldn't matter much. The last board fabricated was of version 3 and I was at ~v3.6 internally due to problems found. I'm now on version for and that last log pointed out numerous issues. R&D is expensive...