Close

"Wide display mode"

A project log for uPD7220 Retro Graphics Card (and VGA hack)

Making an 80s GDC run for the first time in decades, and my first real hack on hackaday.io

dylan-brophyDylan Brophy • 05/09/2024 at 16:20•0 Comments
I found part of the datasheet discussing "wide display mode", which tells the uPD7220 to skip an address each time it loads a word to be displayed.  Here are the relevant sections of the datasheet:As it turns out, I don't think I can get it to add 4 instead of just adding two as described above; this limits my maximum clock speed to 24Mhz (32Mhz on the faster Z7220), so the maximum resolution would be limited by this.  On the other hand, the uPD7220 supports interlacing, so I might be able to push out a higher resolution that way.  Without interlacing under this config, I can't even get to 640x480, but with interlacing I can get at least to 720x480.  I'll have to play with the settings.

I'll need to add a 16-bit register to handle this, since I don't have a real 32-bit bus to load color data from:
I still need to add the logic to generate LD_PIX_TMP, which requires detection of the uPD7220's memory cycles.

The waveforms should look something like this:

The clock at the top is the pixel clock, the fastest it can do is 4x the max GDC clock (so 24Mhz for uPD7220, 32Mhz for certain Z7220 variants).  The third clock from the top is the GDC clock.  The color shift registers load every fourth pixel clock, shown on the 6th signal down from the top.  Each GDC memory cycle we will now be loading 8 pixels instead of just 4, so you see the pixel number reflect this.  Once the address is latched, we can load two words in succession, at twice the GDC clock speed.  To do this, we use the 16-bit register previously mentioned, which loads twice during this single GDC memory cycle, once for each 16-bit word.  The first time it does this, the color shift registers are immediately loaded, thus saving the color data for the first four pixels.  This way, the same 16-bit register can be reused to save the next word.  The LOAD signal to this register is shown as the active-low signal on the bottom of the image above.

Here's the logic I designed to generate this waveform:
As a bonus, I'm including a timing diagram from the datasheet so it is easier to find later:This image details the cycles of various uPD7220 memory accesses, and is super useful for designing the memory control logic.
Previous log

We can certainly make this better.

05/09/2024 at 15:39 • 0 comments
Next log

New Schematic is Nearly Complete

05/10/2024 at 18:55 • 0 comments

Discussions

Yes, delete it Cancel

By using our website and services, you expressly agree to the placement of our performance, functionality, and advertising cookies. Learn More