What a project ! Fantastic !

Mike - very cool project.  How did you keep the tube count so low?  Is it using bit serial arithmetic?

Negative, it's all parallel.  PDP-8 is very simple, all ALU has to do is ADD and AND.  And you get AND as part of ADD (from carries and xoring).  It also has to complement, but you get that with the XOR part of ADD.  It even does carry look-ahead so you could save some tubes by getting rid of that.  And there are only 3 12-bit registers plus state flipflops, gives 50 flipflops total.  I used 3-tube D-flipflops for just about everything, but you could probably reduce tube count by a few dozen by trying pulsed latches (2 tubes per flipflop).

I'm intrigued.  IIRC, the "Straight Eight" used 1500 transistors and 10,000 diodes. 
Have you stripped the CPU down to the bare core functionality.  I guess a lot of the above were for peripheral  and driving and magnetic core memory.

I suppose if you use 3 dual triode tubes per flipflop, that halves the number of "inverters" - compared to the 6 transistors needed for a DFF.

I use the same 6  NAND inverter for my D-FFs, but it has a couple of extra inputs for SET and RESET to make it more like half of a 74xx74.

I have an ALU which also exploits the Sum and Carry outputs of  the full-adder.  I mux between them and you also get ZERO and OR, as well as XOR and AND.  However the ALU is 28 2-input NANDs (transistors) per bit - so that would already use 336 DTL inverters in the ALU.  A-O-I gates might save a few transistors.

Do you use the AND-OR-INVERT gates to generate the XOR and multiplexers.

Ok, well the source, sort of like Verilog, is in the github repo (see source code link) under the modules directory.  One triode plus some diodes makes an AOI gate, so I try to stuff as much as I can in that form.

The tubes are just the processor, no memory or peripherals, those are done by the RasPI.  When the tubes detect any IOT, Group 2 with HLT or OSR, or Group 3, they tell the RasPI to process the instruction as an I/O instruction.  All other instructions are fully processed by the tubes.

Extremely cool project!

Hey thanks.  BTW, I noticed Nixies on your page.  I was thinking of making a Nixie frequency counter for my display instead of the 7-seg LEDs.  I use an Arduino and multiplex the LEDs to reduce pin count.  I'm wondering how well multiplexing works with Nixies.  Do you know if they are bright enough when multiplexed, given that they would only be powered 20% of the time?

Hello Mike,

Multiplexing works well, but it would require some additional circuitry. Some time ago, I used the k155d1 nixie driver and multiplexed 4 nixies. I know it also works well for 6 nixies.

-Shameless Self-Promotion Alert -
The Kickstarter nixie drivers you saw are Arduino-compatible (library available), are powered from 5V, and are 'daisy-chain-able', so you can use only 4 data pins to fully control any number of them. It's probably the simplest way to drive nixies now, consider checking them out on Tindie since they are on sale: https://www.tindie.com/products/allexok/easynixie/

Kickstarter link: https://www.kickstarter.com/projects/esp32-stick/easynixie

thanks I'll have a look

Wow! Very impressive. This is a classic.

Thanks.  Same Nixie question, have you tried multiplexing them?  Are they bright enough?  And any other issues multiplexing?

I have not tried personally but it's possible. Naturally you have increase the current to compensate for the duty cycle. The calculator I extracted my remaining stash of nixies from used multiplexing. There are 16 so the duty cycle was down to 6.25%.

I don't know enough about nixies to say which models tolerate muxing better than others. I'll stick with static drive as I have only one batch left and I won't buy any NOS after that. Also just like with other display technologies muxing means more wiring in return for less driver chips. Plus you have to mux the high side too.

In case you haven't discovered it yet, my #Modularnixie project reduces the signal wiring by using shift registers but still using static drive for the nixies.