CPLDs, FPGAs, and hard bootloaders

A contest log for The 1kB Challenge

The only limit is what you can do with 1 kB of program memory

Adam FabioAdam Fabio 11/23/2016 at 03:150 Comments

It's come to my attention that the rules excluded a few architectures which have bootloaders hard coded to run at powerup. An example of this is the parallax propeller, which must run the spin interpreter before firing off a PASM routine. The spirit of the rules is leveling the playing field - not excluding any particular processor. As such I've updated the rules to allow hard coded bootloaders. Check it out!

Quite a few people have been asking about CPLDs and FPGAs. First off, custom processors instantiated in FPGA's are allowed, and encouraged! CPLD/FPGA external logic is also perfectly fine to use, but remember this is a contest about fitting a lot of function into a little codespace. A ton of perfectly executed Verilog or VHDL code to implement a state machine won't impress the judges as much as a well crafted 1 kB routine. The same goes for Analog or even mechanical entries. Don't worry - there are more contests coming down the pipe for your analog and mechanical hacks!