Stephen TranovichOkay, let's get started! A BIG welcome to @Al Williams for coming on the Hack Chat to talk FPGA with us!
Thanks Stephen and thanks everyone for jointing
joining rather
@Al Williams , kick us off by telling us a little about yourself!
Well most of you probably read some of my stuff on Hackaday but I've been doing electronics for the majority of my life -- ever since I was a kid. I had a ham radio license in 1977....
Hi @Al Williams and @Stephen Tranovich :-)
And when I went to school there were no FPGAs
So later when I got interested I tried really hard to learn about them and there were 2 or 3 things I just couldn't get. So I finally broke down and took one of the freebie seminars from Altera
If I could have just asked the guy those 3 things it would have taken 15 minutes
But I had to take the whole class ;-)
So since then I've really looked for ways to bring more people into FPGAs and make them more accessible. The costs have come down both of the parts and the tools
most of the tools are free and we have Open Source for at least one FPGA family now
The bootcamps are one way I wanted to try to make things easier for people to climb that learning curve
That's awesome. And they sure are helping.
FPGAs aren't for everything, of course. Neither is an AVR processor or a 555 chip. But it is a great trick to have in your toolbag and when you do need it almost nothing else will do short of building huge racks of logic circuits
And this is everyone's chance to ask you their own 3 questions!
So before we start...
If you know me, you know I’m always a little different. This is going to be a unique Hackchat because I’m going to flip it around. Sure, I’ll take questions, but I’m very interested in asking you questions. For example:
Have you tried the FPGA bootcamps? Why or why not?
What FPGAs would you like to see us cover? (Currently, only ice40)
What topics would you like to see in the future? More FPGA topics? Other topics?
If you haven’t heard, we released bootcamp #4 today which is all about developing state machines in Verilog. This is another one where you don’t really need the hardware to follow along -- you can do everything in your browser or an offline Verilog simulator like Icarus.
The next two will build on the state machine premise and we’ll build a serial to PWM “chip” that you could actually use (probably with the ice40 again, but maybe also with the MAX10, or other FPGAs depending on your feedback).
So… who’s taken any of the bootcamps?
Well while you are thinking... I see @Thomas Shaddack has a question about command line tools
Sure, here's @Thomas Shaddack 's question: Are there some commandline tools for FPGAs? Something that would not require a heavyweight multigigabyte GUI monstrosity just to compile a verilog or vhdl source, and could be run from a console?
That's one thing I like about the open source tools is they are command line and that's it! However, there's a secret about the tools
Tell us the secret!
All the vendor tools are GUI shells over a bunch of command line programs, TCL scripts, and Perl scripts
only found out about the bootcamps today... as a result of the email to join this chat, but will get stuck in as they have always interested me
So for example if you use Xilinx: https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_5/devref.pdf
Or Altera: https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/an/an309.pdf
Don't know why that's a JP link
but it is in English
So you can easily build your own tool scripts, use Makefiles, build from emacs (I do that).
The Lattice open source tools (iceStorm) has really picked up a lot of capability
https://hackaday.com/2018/10/03/icestorm-tools-roundup/
Icestorm Tools Roundup: Open Source FPGA Dev Guide
We like the ICE40 FPGA from Lattice for two reasons: there are cheap development boards like the Icestick available for it and there are open source tools. We've based several tutorials on the Icestorm toolchain and it works quite well. However, the open source tools don't always expose everything that you see from commercial tools.
You might read that article about all the tools that are now up and also my command line driver for them is linked there on GitHub.
What FPGA family do you use @Thomas Shaddack ?
I learned about the FPGA bootcamp a few weeks ago. Haven't had time to go through them yet. I picked up three inexpensive FPGA boards. Two are Spartan 3 and the other is Spartan 6. In reading about Verilog and VHDL I went with VHDL.
Hi Kevin. Well that's the old vi/emacs pc/mac debate isn't it?
Pretty much. :)
@Al Williams none yet. tried to putz with some rudimentary CPLDs from Xilinx and one lower-end thing from Altera, available as cheapo Chinese boards on ebay.
My day job used to be with Boeing and we had to use a lot of VHDL because the government likes it. But most people I know prefer Verilog. With the modern extensions to Verilog the two are pretty much feature equivalent. But it just depends. Verilog is kind of C-like and VHDL is kind of Ada like
There are converters that can go either way but they are typically not great
I think VHDL is better, because it catches more bugs at compile time. Verilog is to lax with implicit type conversions etc.
Depends on your tools though don't you think? And if you do a lint step.
i don't have a FPGA /toolchain as yet and would welcome a recommendation on what best to follow along
Well the Bootcamps right now assume you have an icestick which is a Lattice ice40 for about $30 and very easy to set up
needing an extra lint step proves my argument :-)
I have one Spartan 3 board driving a set of 8 7-segment displays wired up for Charlieplexing (9 wires to control 64 segments). I'm using that display for my introduction to using VHDL.
I will go through the bootcamps when I an going to learn Verilog. I speak VHDL only at the moment.
I am about to do a post with a hands on with the version 2 of the Upduino which is really cheap like $12
I have found that learning VHDL then Verilog or vice versa isn't a big deal. The real big deal is changing how you think
for example...
using Verilog...
true
a<=10;
b<=a;
Does NOT necessarily mean b==10! That usually shocks people for a few days or weeks.
Before we spend the while chat debating VHDL vs Verilog, let's take another community question! This question is from @Christoph : Where could I look for open source "hardware snippets" of decent quality, like an SPI?
I'd like to create a frame buffer that receives a packed monochrome frame (1 bit per pixel) via SPI and outputs a 16-bit per pixel (fixed color) frame to an SPI display.
The Upduino is very cool although the board is a bit of a mess. But it has the bigger Lattice part on it which is nice and I'm a big fan of iceStorm
you could do a ":=" in VHDL
Yeah or an = in Verilog but...
just a shock
Great question @Christoph
One of the best and worst places to look is Open cores: https://opencores.org/
I say best because everything is there
I say worst because everything is there ;-)
@Frank Buss I don't remember specifically what it was about VHDL that pointed me in that direction but what I read made me thing it was the better choice. IIRC, VHDL helps avoid some (timing?) problems you can have with Verilog. At the same time I know that in North America Verilog is the more common HDL for use with FPGAs. I've also seen a site online that will convert between Verilog and VHDL.
A little more cut and past snippet is on GitHub https://github.com/pConst/basic_verilog
Of course, like anything what you find on the Internet is of varying quality
sturgeon's law.
I thought so, too. I guess as more and more hobbyists use FPGAs, github will see more fpga code
The vendors call little blocks like that IP -- or Intellectual Property and
I don't think VHDL vs. Verilog helps with timing problems, but it definitely can help with other problems
Many times there is a vendor solution for things like UARTs or SPI and those are generally good quality and well documented
Good example... remember the Hackaday article on using the MAX1000 as a POV display?
https://hackaday.com/2018/08/31/max1000-tutorial-is-quite-persistent/
Learn FPGA with this Persistence of Vision Hack
Everybody wants to give FPGA development a try and here's a great way to get into it. You can build your own Persistence of Vision display using a $30 dev board. It's a fun project, and you'll learn quite a bit about designing for an FPGA, as well as using the Quartus design software.
maybe, for that specific case (SPI), I just didn't find the vendor's SPI
Then I enhanced it with a serial port
https://hackaday.com/2018/09/06/fpga-pov-toy-gets-customized/
How to Add UART to Your FPGA Projects
Being able to communicate between a host computer and a project is often a key requirement, and for FPGA projects that is easily done by adding a submodule like a UART. A Universal Asynchronous Receiver-Transmitter is the hardware that facilitates communications with a serial port, so you can send commands from a computer and get messages in return.
Read the comments on that last one.
I used a UART "from the Internet" that I've used before and I couldn't find the exact version online that I was using. So I posted mine, but to give credit I linked to the "old version" on GitHub.
Well the old version had many problems.
I don't remember if I fixed it (and that's why I can't find it) or if someone else fixed it, I took it and now can't find the link
But you do have to do a little due diligence when you pick up someone else's code
I did not have the time to work through the bootcamps yet. But big thanks for putting them together. I will definitely see if I can streamline and adapt them to the iCEBreaker that we are working on. :) It is a great resource. :)
of course
Thanks @Piotr Esden-Tempski -- yeah I think if more people knew how cheap the ice family was, low power, and the availability of good free tools, we'd see a lot more of it. I'm glad you are building more with it.
I see @MagicWolfi has a question
Also @Al Williams what do you think about the higher level solutions like migen. I spent some time with it recently and it is great to have a generator language at the fingertips to create repetitive logic.
@Piotr Esden-Tempski Great question. Give me a minute to work through some of the submitted ones
@MagicWolfi asks about bus structures for connecting modules
@Al Williams is calling for @MagicWolfi 's question! What standard bus structure would be recommended to connect modules for routing data between them. Any differences for continuous data streams vs. blocks of data at random times?
At the end it is still Verilog at the backend, but the generator does not make typos as much as I do and keeps the lack of compiler complains away from me. :)
Remember the opencores site I just linked? On there you'll find a spec that's open for Wishbone which is a simple nice interconnect. If you are doing something open source and that's good enough then it helps to use that. You can reuse a lot of IP
@Piotr Esden-Tempski Feel free to submit your question in the discussion section here so that we can answer it in turn! https://hackaday.io/event/161622-fpga-bootcamp-hack-chat
anybody taking part in the RISCV softCPU contest?
hey antti
Now there are two things to consider
@Stephen Tranovich Yes right. sorry. :)
yes, I have a pretty nice idea to make the core really small, but I don't know if they think it would be cheating :-)
If you have an ARM core either soft or on die then you get milage out of using the ARM busses which the vendor probably gives you (e.g., AXI, etc.)
But if you need a high speed bus... and interconnect, you might look at what Opal Kelly is doing which is "open" called Syzygy https://syzygyfpga.io/
Hi Frank, I wrote to riscv mailinglist
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