Lutetiumyeah, 6 weeks is very short
the RULES are bullshit, I can say it here..
I haven't looked at them lately but I will
how many days would you need to figure out WHAT is needed to qualify?
So @MagicWolfi does that help?
I have spent 2 full days, I am halfway there to know what I should do.. the rules are not strict enough
I think I can still do it, with my idea :-)
@Stephen Tranovich who's next?
@Antti Lukats we're in the middle of a Hack Chat right now. Could you continue your conversation in half an hour?
@Al Williams before we hop into the next question, would you like to ask the group another question of yours?
this is FPGA.. !!!
yes I go off, thank you for the nice word, I will not forget.
bye.
lol
Hey @Antti Lukats let me get through some more questions and we'll open up to that towards the end while folks are still here
Ok, so my question back to everyone is if we were to do more FPGA-specific bootcamps are you happy with them being ice40 or would you rather see MAX10 or Xilinx or ??? -- whath are you guys using most of?
Yes I am fine with iCE40, but I am biased. ;)
Spartan 6 is my go to part.
Keeping in mind that most of the bootcamps are agnostic. So I've thoughth about doing a 3A where we deploy the same code to say MAX1000
I guess ice40 is a good start, and people can progress from there
I don't care, but the boot camp is a good idea. Will there be more advanced stuff discussed like meta stability etc. as well?
The nice thing is ice40 is so cheap
I currently use Altera products but because of the bootcamps I have started learning ice40
so I vote keeping it
so buy a $20 board and 90% of what you learn will transfer over to Altera/Xilinx etc.
Like I say the Upduino is even cheaper
I think fundamental is the ease of access. So iCE40 and soon ECP5 is the way to go. Definitely not Altera. Maybe Xilinx 7 series eventually.
and mostly works the same. Has a few more features. Needs a slightly different build script
What is the Upduino price?
altera is fine too.
The only reason I keep looking at MAX10 is that a) Arrow has that cheap board (not really Arrow but they sell it) and b) the Arduino Vidor uses it
@Al Williams The camps would be more directly relevant to me if they were for Spartan 3 or 6. It really depends on whether the example code is using something specific to the ice device.
The Upduino 2 is like $13 or $14. Don't get the version 1
Well like I say Kevin, all but #3 (right now) are FPGA agnostic
max1000 is my design, not much to be proud of but relativly cheap :)
how much is the postage for the upduino for those of us stuck in Europistan?
@Al Williams could you talk about your experience with SoC FPGAs? Currently I am starting to play around with the Cyclone V SoC on a DE10-Nano board.
All simulation and you move from there. I love love love EDA Playground for that because you are ready to go with zero software. But I also support Icarus/gtkwave and I have been using cvc too
@Antti Lukats I didn't know if that was a secret but yes, I saw that. The docs on your site are better than Arrow's lol
we are so short on time documents
@Thomas Shaddack I don't know... http://gnarlygrey.atspace.cc/development-platform.html
we would LOVE LOVE LOVE to give away lots of FPGA hardware for those who would play with it.. for little exposure, demo design and docu
@Antti Lukats That's good for us because it gives us something to write about lol
Found it... Not sure if the link was already posted:
The last board you sent me caught me mid divorce so I dind't get much chance to play with it lol
sorry, hope it wasnt the reason 4? :)
I think that if you standardize on apio for example you will get an easy toolset with a gui and noone can complain about it because the dev boards are very affordable. Most of the excersizes will be translatable to any FPGA. I think it is important to make an executive decision on that because everyone is either forced or chooses to use any kind of FPGA.
Actually if you were I'd send you a thank you card!
@Bonki I've used the Cyclone SoC, in combination with NIOS some years ago. As usual, the tools can be a pain sometimes, but pretty nice to click visually your own system with the peripherals you like, and then the code for NIOS is automatically generated etc.
I always end up with a hundred tabs open at the end of these chats!
@Al Williams does that give you a good picture of what people are using? Ready for another community question?
Yes, let's go
This next one if from @Eric Sherk : Can you talk about design verification both pre- and post- FPGA implementation?
NIOS is simple, but for the ARM SoC I'd use Xilinx ZYNQ not altera SoC..
(Yes to ZYNQ I was going to mention that when I got there)
yes, the Zynq is awesome, I did a 64 channel / 100 MHz logic analyzer with the parallela with it once:
http://www.frank-buss.de/parallella/sampler/
today ZYNQ support both on the FPGA side as on the linux side is superior compared to the altera path
As to Eric's question... Verification is great although because FPGAs are easier to respin you don't have to get quite as torqued as the ASIC guys do about it. But it still pays off... so generally
if only Vivado wouldn't suck that much :-)
I will try to build up a good testbench and some assertions and run the code through Modelsim or Icarus or cvc (anyone else using cvc? -- very fast)
@Frank Buss let's hope that this will not be a problem in the near future. ;) https://github.com/SymbiFlow/prjxray
To piggy-back off that question, @Piotr Esden-Tempski asks: Do you have experience with formal verification? Have you used the Yosys formal verification capabilities yet?
So by the time I put it in chip I am pretty happy usually. If I'm using the big tools I will often do a post sim also but those are painful. If you haven't done that, that's where your Verilog is chewed down to primatives
and you simulate that which with the right libraries and models can tell you a lot if you are trying to optimize speed or power but without the right models isn't that useful
I have not used the Yosys formal verification yet, although I have had some experience with that with expensive tools during my day job
If you look at Hackaday today
I posted part 1 of a two parter that talks about Verifla
you could simulate the modules separately, but of course, this wouldn't take into account the full routing
which is a Verilog Logic Analyzer like Chipscope or Signal Tap but Open Source
I didn't write it but I did fork it and make a lot of significant bug fixes and improvements
So I can now program with iceStorm (or the Altera tools on MAX1000) and pull data off the real FPGA to show in gtkwave
which is pretty slick
Should port to Xilinx easily. Odd
It is very easy to add SUMP to your design, also a great solution to read out the internal state of your design from the FPGA.
Yosys does system verilog features that Altera doesn't like putting defaults in a parameter list
three cheers for debug tools right in the design!
Yes although SUMP is not tiny and it is nice having the same wave tool for simulation and live debug
So check that article out and look for part 2 as soon as I finish it
https://hackaday.com/2018/10/12/logic-analyzers-for-fpgas-a-verilog-odyssey/
Logic Analyzers for FPGAs: A Verilog Odyssey
Sometimes you start something simple and then it just leads to a chain reaction of things. I wanted to write a post about doing state machines in Verilog and target the Lattice iCEstick board that we often use for quick FPGA projects. That led to a small problem: how do you show what's going on inside?
No definitely simulation is essential, and SUMP does not replace that, it is a supplement to address issues at the end of the design process.
Who's using verification frameworks like OVM (is it OVM?)
@Piotr Esden-Tempski has another question for you: What do you think about generator toolkits like migen or Chisel?
we use UVM at my day job, OVM is precursor
Yes I remember @Piotr Esden-Tempski asking that. Well, it depends. There's been a lot of attempts to convert HDL a lot of different ways. The vendors are all happy about writing C and pushing HDL out -- we've talked about some early efforts on that in HaD.... and there's migen and then whole new languages like Spinal etc. I would almost think it is like programming languages.... you might have your favorite. But it is probably best to teach/learn one of the big ones.
UVM... that's what I was thinking of...
I knew that didn't sound quite right
So just like it is probably better to teach a new programmer simple C, that guy might go on to write only with the Qt toolkit
but learning the Qt way first is distracting, hides a lot from you, and makes it hard to go sideways
So what other topics do you think we should be investing in the bootcamp format? FPGA topics or otherwise?
Good question, @Al Williams !
I will tell you we have at least two more FPGA coming... one will be step by step building a UART and then we will use the UART to do a PWM peripheral that would actually be practical
And the new one out today does a pretty broad coverage of state machines
which we will use in the UART
so what do you want to see?
Is the UART going to be a 16550 flavor?
I doubt we will go that far, but maybe. I haven't written it yet. You can probably find 16550 IP on OpenCores although I haven't looked
https://opencores.org/project/uart16550
UART 16550 core :: Overview :: OpenCores
uart16550 is a 16550 compatible (mostly) UART core. The bus interface is WISHBONE SoC bus Rev. B. Features all the standard options of the 16550 UART: FIFO based operation, interrupt requests and other. The datasheet can be downloaded from the CVS tree along with the source code.
When you do PWM, make sure to cover PDM too. It is interesting how they differ depending on the amount of outputs you need. ;)
Yes. Well you guys probably don't remember my PAK-V chip (which was not an FPGA just a screaming fast SX processor)
but it did 8 channels of PWM like that and could do PWM/PDM -- wound up in some surprising places
I looked a few years ago. Found lots of half started, and partially implemented projects.
There are a ton but like you say I don't know how many of them are useful
If you do the Google custom search for 16550 on their site....
So what other topics are you interested in for Bootcamps
I know @Sophi Kravitz will be taking notes
is the official hack chat over?
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