Close

Hack Chat Transcript, Part 2

A event log for SkyWater PDK Hack Chat

Absolutely fabless

Dan MaloneyDan Maloney 09/16/2020 at 20:170 Comments

Tim Ansell12:44 PM
@Troy Benjegerdes My general thinking is that if 130nm is successful I will be able to convince foundries to open source more advanced nodes where a Linux class processor is a *lot* more interesting.

Mohamed Kassem12:44 PM
"steve" what's your @ ID can't find you?

Nathan Kohagen12:45 PM
The Skywater fab in Minnesota was the main Cypress Semiconductor fab. The PSoC3 (8051) and PSoC5 (ARM Cortex M3) family of chips (which I was one of the designers of) were on this 130nm process. And regarding the cryo question earlier in this chat, to my knowledge this 130nm process has not been characterized down to cryo temps. It is public knowledge that the DWave (quantum computing) superconducting (cryo) chips were fabbed at the Cypress Minnesota fab a decade ago so the fab is capable of more exotic fab process recipes. Another note: the Skywater fab is a secure fab (has information control policies) that allows it to be used for chips that are strategically important to US national security. That fab is a very important fab to the future of the US semiconductor industry.

Troy Benjegerdes12:45 PM
@Tim Ansell you are probably right, unless I can build a single wafer that boots linux with 8TB of 3-d non-volatile ram ;)

steve12:46 PM
@steveulti

Mohamed Kassem12:46 PM
@Nathan Kohagen I second that ..

Tim Ansell12:46 PM
The great thing about open source, and something I want to promote, you don't have to ask for permission - you can just go do things I'm not directly interested in without needing to chat with me.

Troy Benjegerdes12:46 PM
@Art Scott you mention Posit.. my first job in College was working for John Gustafson

Mohamed Kassem12:46 PM
-----------------------

Full Open Source RTL2GDS Compiler

https://github.com/efabless/openlane

Open Source Manufacturable 130nm PDK

https://github.com/google/skywater-pdk

----------------------------

Tim Ansell12:47 PM
My goal is to build a thriving ecosystem of people doing everything from pretty "boring" things to crazy stuff like the adiabatic circuits that @Art Scott is super interested in.

Patrick Van Oosterwijck12:48 PM
Much more interesting than another Linux bootable micro which you can have for $5 nowadays...

Mohamed Kassem12:48 PM
@Steve very soon

Tim Ansell12:49 PM
Someone asked earlier about documentation on the analog side of things

Troy Benjegerdes12:49 PM
so who can help me write a Posit unit for rocket-chip

Mohamed Kassem12:49 PM
@Steve we are finishing the IO's so we can push several chips including Caravel

Troy Benjegerdes12:49 PM
(or vhdl to plug into leon-sparc or noel-RiscV from Gaisler's GRLIB)

Tim Ansell12:49 PM
I have a "work in progress" pull request for the repo at https://github.com/google/skywater-pdk/pull/136 which adds a lot of detail about the various supported devices

Steve Kelly12:49 PM
@Mohamed Kassem is the base SoC for the initial shuttle decided?

Patrick Van Oosterwijck12:50 PM
@Tim Ansell thanks for the link to that PR

Mohamed Kassem12:50 PM
@Steve Kelly call it 75>#/span###

W5VO12:50 PM
Does this process variant support some of the BCD / analog devices that Skywater offers?

W5VO12:51 PM
oh, just saw that.

Tim Ansell12:51 PM
The devices included are;

Bipolar (NPN)

Bipolar (PNP)

MiM Capacitor

Vertical Parallel Plate (VPP) capacitors

SONOS cells

SRAM cells

Diodes

11V/16V NMOS FET

1.8V NMOS FET

1.8V low-VT NMOS FET

20V NMOS FET

20V isolated NMOS FET

20V native NMOS FET

20V NMOS zero-VT FET

3.0V and 5.0V native NMOS FET

5.0V/10.5V NMOS FET

NMOS ESD FET

10V/16V PMOS FET

1.8V PMOS FET

1.8V high-VT PMOS FET

1.8V low-VT PMOS FET

20V PMOS FET

5.0V/10.5V PMOS FET

Generic Resistors

P- poly precision resistors

P+ poly precision resistors

Varactors

Tim Ansell12:52 PM
I want to get the PR merged ASAP but it still needs some finishing touches.

Art Scott12:52 PM
@Troy Benjegerdes posithub PACoGen

PACoGen: Posit Arithmetic Core Generator .... verilog file ... lets do it

Sam Ellicott joined the room.12:53 PM

Mohamed Kassem12:53 PM
join us here if you haven't yet ....https://join.skywater.tools

Steve Kelly12:54 PM
@Tim Ansell whats the likelihood we get a "Sky130" target in something like symbiflow (if not already)?

Tim Ansell12:54 PM
The current open source analog IP for SKY130 is pretty limited, but the analog models where only released yesterday and there are about ~250 people in the #analog-design slack channel so I'm hopeful we will see a bunch of interesting stuff very soon.

Mohamed Kassem12:55 PM
Building on the ecosystem comment by @Tim Ansell - as a community we should allocate energy to get the critical mass of functions designed under apache 2.0

Sam Ellicott12:55 PM
@Tim Ansell Are the bipolar capacitors horizontal or vertical?

Tim Ansell12:56 PM
@steve The OpenFPGA team at University of Utah (https://sites.google.com/site/pegaillardon/research/openfpga) recently committed to doing an "iCE40" sized FPGA on SKY130.

Sam Ellicott12:56 PM
Edit on my question: *Bipolar transistors

Tim Ansell12:57 PM
SKY130 technology is around ~Virtex II technology if I understand correctly -- so it won't be a super fancy FPGA

Tim Ansell12:58 PM
But it will be an FPGA with open source tooling (Yosys+VPR) taped out on an open source PDK (skywater-pdk). Hopefully in the future it will even use the open source ASIC tools rather than the proprietary tools.

Mohamed Kassem12:59 PM
@Sam Ellicott --- only parasitic bipolar

Patrick Van Oosterwijck1:00 PM
Are there basic IP like OPAMPs, comparators, bandgap reference provided or is that up to the user?

Tim Ansell1:00 PM
@Patrick Van Oosterwijck Currently up to the user -- but we are hoping to end up with some designs under a compatible license that can be included

We're getting close to 1:00 here, which means we have to wrap the officil part of the chat up. The chat is always open, though, so feel free to carry on the conversation. For now, we just need to thank Tim, Michael, and Mohamed for their time today and for the deep dive into PDKs.

And thanks all for dropping by the Hack Chat today with so many excellent questions.

Nyles1:01 PM
Thank you!

Tim Ansell1:01 PM
@Patrick Van Oosterwijck We are also looking into "analog generator" technologies like FASoC (from Uni of Michigan) and BAG from Berkeley as a way to get further analog IP

Jay Morreale1:01 PM
Thank you. Very interesting work.

Patrick Van Oosterwijck1:01 PM
Ooh that would be interesting

LesWright1:01 PM
Thank you. This is truly outstanding work!

Tim Ansell1:03 PM
Once we have both an open source ASIC flow and open source FPGA generator it will be much easier to "turn the knob" between soft (FPGA) and hardened (ASIC) design

Art Scott1:03 PM
Is it possible to use your RISCV core to run tests programs on project(s) ... say test vectors?

Tim Ansell1:04 PM
@Art Scott hopefully!

Art Scott1:04 PM
@Tim Ansell That would be nice!

Tim Ansell1:04 PM
Pretty much everything in the open source RTL design currently goes through Yosys from Claire Wolf (https://github.com/YosysHQ/yosys)

Troy Benjegerdes1:05 PM
Will the Utah team be releasing designs? What would it take to port there material to OpenLane EDA flow

Art Scott1:06 PM
Yosys is solid. And the ongoing work is too.

Tim Ansell1:06 PM
So a big thank you to Claire for all her work on developing that project to were it is now

Troy Benjegerdes1:07 PM
How much memory do we expect YOSYS might take to synthesize a linux-capable core

Tim Ansell1:07 PM
@Troy Benjegerdes Yeap, all the RTL and everything will be released. It's not a "hard" problem but the type of designs found in FPGAs tend to cause place and route solutions to choke a bit

Art Scott1:07 PM
VLSI ... Very Large Scale INTERCONNECT

Tim Ansell1:08 PM
@Troy Benjegerdes - 8gig --> 16gig maybe?

Nathan Kohagen1:08 PM
Thank you for the great work you are doing! This is awesome to have an open sourced fab process!

Troy Benjegerdes1:08 PM
and if I were to be stupid and use SRAM on SKY130, how much silicon area would I burn instantiating 24GB of SRAM

Tim Ansell1:09 PM
@Troy Benjegerdes With how cheap DDR memory is these days, it doesn't make much sense to care about memory usage until it gets to the >256gig space. Developer effort to save that memory is much more expensive.

Michael Gielda1:09 PM
@Nathan Kohagen you seem to be involved with some cool stuff yourself. Glad you appreciate this.

Troy Benjegerdes1:10 PM
@Tim Ansell if you can point me to a Sky130 silicon proven DDR controller, I might agree with you. But then I still have to do the PCB layout which is no fun

Michael Gielda1:10 PM
and congrats on having actually worked on some of the chips in question :) we could use your help!

Tim Ansell1:10 PM
@Troy Benjegerdes -- According to my inspiration document SRAM cells on 130nm seem to average around ~2.45 µm2

Karol Gugala joined the room.1:10 PM

Troy Benjegerdes1:11 PM
and how man 2.5um2 cells can I put on a single SKY130 wafer

Troy Benjegerdes1:11 PM
many

Tim Ansell1:12 PM
@Troy Benjegerdes The 130nm process generally uses 300mm diameter wafers but reticle size is much smaller than that...

Troy Benjegerdes1:12 PM
@Tim Ansell I would rather spend my time on OpenLane, memory optimization, and a 'system on a wafer', along with how to interconnect different reticles ;)

W5VO1:13 PM
Hunting for Cerebras's "Largest Die" title?

Troy Benjegerdes1:13 PM
than try to have to deal with all the complexity in a DDR controller.

Tim Ansell1:13 PM
PIC PIC32MZ2048ECH100 -- 5800 x 5500 μm (31.9 mm2)

16 Kilobytes I-Cache / 4 Kilobytes D-Cache -- 512 KB of SRAM -- 2 MB of NOR flash + 160 KB of Boot Flash

Troy Benjegerdes1:13 PM
oh, and memory load latency across a wafer is going to be a lot better than 70+ns for DRAM pre-charge

Discussions