@Troy Benjegerdes My general thinking is that if 130nm is successful I will be able to convince foundries to open source more advanced nodes where a Linux class processor is a *lot* more interesting.
@ ID can't find you?"steve" what's your
The Skywater fab in Minnesota was the main Cypress Semiconductor fab. The PSoC3 (8051) and PSoC5 (ARM Cortex M3) family of chips (which I was one of the designers of) were on this 130nm process. And regarding the cryo question earlier in this chat, to my knowledge this 130nm process has not been characterized down to cryo temps. It is public knowledge that the DWave (quantum computing) superconducting (cryo) chips were fabbed at the Cypress Minnesota fab a decade ago so the fab is capable of more exotic fab process recipes. Another note: the Skywater fab is a secure fab (has information control policies) that allows it to be used for chips that are strategically important to US national security. That fab is a very important fab to the future of the US semiconductor industry.
@Tim Ansell you are probably right, unless I can build a single wafer that boots linux with 8TB of 3-d non-volatile ram ;)
@Nathan Kohagen I second that ..
The great thing about open source, and something I want to promote, you don't have to ask for permission - you can just go do things I'm not directly interested in without needing to chat with me.
@Art Scott you mention Posit.. my first job in College was working for John Gustafson
Full Open Source RTL2GDS Compiler
Open Source Manufacturable 130nm PDK
@Art Scott is super interested in.My goal is to build a thriving ecosystem of people doing everything from pretty "boring" things to crazy stuff like the adiabatic circuits that
Much more interesting than another Linux bootable micro which you can have for $5 nowadays...
@Steve very soon
Someone asked earlier about documentation on the analog side of things
so who can help me write a Posit unit for rocket-chip
@Steve we are finishing the IO's so we can push several chips including Caravel
(or vhdl to plug into leon-sparc or noel-RiscV from Gaisler's GRLIB)
https://github.com/google/skywater-pdk/pull/136 which adds a lot of detail about the various supported devicesI have a "work in progress" pull request for the repo at
@Mohamed Kassem is the base SoC for the initial shuttle decided?
@Tim Ansell thanks for the link to that PR
@Steve Kelly call it 75>#/span###
Does this process variant support some of the BCD / analog devices that Skywater offers?
oh, just saw that.
The devices included are;
Vertical Parallel Plate (VPP) capacitors
11V/16V NMOS FET
1.8V NMOS FET
1.8V low-VT NMOS FET
20V NMOS FET
20V isolated NMOS FET
20V native NMOS FET
20V NMOS zero-VT FET
3.0V and 5.0V native NMOS FET
5.0V/10.5V NMOS FET
NMOS ESD FET
10V/16V PMOS FET
1.8V PMOS FET
1.8V high-VT PMOS FET
1.8V low-VT PMOS FET
20V PMOS FET
5.0V/10.5V PMOS FET
P- poly precision resistors
P+ poly precision resistors
I want to get the PR merged ASAP but it still needs some finishing touches.
@Troy Benjegerdes posithub PACoGen
PACoGen: Posit Arithmetic Core Generator .... verilog file ... lets do it
@Tim Ansell whats the likelihood we get a "Sky130" target in something like symbiflow (if not already)?
The current open source analog IP for SKY130 is pretty limited, but the analog models where only released yesterday and there are about ~250 people in the #analog-design slack channel so I'm hopeful we will see a bunch of interesting stuff very soon.
@Tim Ansell - as a community we should allocate energy to get the critical mass of functions designed under apache 2.0Building on the ecosystem comment by
@Tim Ansell Are the bipolar capacitors horizontal or vertical?
@steve The OpenFPGA team at University of Utah (https://sites.google.com/site/pegaillardon/research/openfpga) recently committed to doing an "iCE40" sized FPGA on SKY130.
Edit on my question: *Bipolar transistors
SKY130 technology is around ~Virtex II technology if I understand correctly -- so it won't be a super fancy FPGA
But it will be an FPGA with open source tooling (Yosys+VPR) taped out on an open source PDK (skywater-pdk). Hopefully in the future it will even use the open source ASIC tools rather than the proprietary tools.
@Sam Ellicott --- only parasitic bipolar
Are there basic IP like OPAMPs, comparators, bandgap reference provided or is that up to the user?
@Patrick Van Oosterwijck Currently up to the user -- but we are hoping to end up with some designs under a compatible license that can be included
We're getting close to 1:00 here, which means we have to wrap the officil part of the chat up. The chat is always open, though, so feel free to carry on the conversation. For now, we just need to thank Tim, Michael, and Mohamed for their time today and for the deep dive into PDKs.
And thanks all for dropping by the Hack Chat today with so many excellent questions.
@Patrick Van Oosterwijck We are also looking into "analog generator" technologies like FASoC (from Uni of Michigan) and BAG from Berkeley as a way to get further analog IP
Thank you. Very interesting work.
Ooh that would be interesting
Thank you. This is truly outstanding work!
Once we have both an open source ASIC flow and open source FPGA generator it will be much easier to "turn the knob" between soft (FPGA) and hardened (ASIC) design
Is it possible to use your RISCV core to run tests programs on project(s) ... say test vectors?
@Art Scott hopefully!
@Tim Ansell That would be nice!
Will the Utah team be releasing designs? What would it take to port there material to OpenLane EDA flow
Yosys is solid. And the ongoing work is too.
So a big thank you to Claire for all her work on developing that project to were it is now
How much memory do we expect YOSYS might take to synthesize a linux-capable core
@Troy Benjegerdes Yeap, all the RTL and everything will be released. It's not a "hard" problem but the type of designs found in FPGAs tend to cause place and route solutions to choke a bit
VLSI ... Very Large Scale INTERCONNECT
@Troy Benjegerdes - 8gig --> 16gig maybe?
Thank you for the great work you are doing! This is awesome to have an open sourced fab process!
and if I were to be stupid and use SRAM on SKY130, how much silicon area would I burn instantiating 24GB of SRAM
@Troy Benjegerdes With how cheap DDR memory is these days, it doesn't make much sense to care about memory usage until it gets to the >256gig space. Developer effort to save that memory is much more expensive.
@Nathan Kohagen you seem to be involved with some cool stuff yourself. Glad you appreciate this.
@Tim Ansell if you can point me to a Sky130 silicon proven DDR controller, I might agree with you. But then I still have to do the PCB layout which is no fun
and congrats on having actually worked on some of the chips in question :) we could use your help!
@Troy Benjegerdes -- According to my inspiration document SRAM cells on 130nm seem to average around ~2.45 µm2
and how man 2.5um2 cells can I put on a single SKY130 wafer
@Troy Benjegerdes The 130nm process generally uses 300mm diameter wafers but reticle size is much smaller than that...
@Tim Ansell I would rather spend my time on OpenLane, memory optimization, and a 'system on a wafer', along with how to interconnect different reticles ;)
Hunting for Cerebras's "Largest Die" title?
than try to have to deal with all the complexity in a DDR controller.
PIC PIC32MZ2048ECH100 -- 5800 x 5500 μm (31.9 mm2)
16 Kilobytes I-Cache / 4 Kilobytes D-Cache -- 512 KB of SRAM -- 2 MB of NOR flash + 160 KB of Boot Flash
oh, and memory load latency across a wafer is going to be a lot better than 70+ns for DRAM pre-charge