Matt Martin Shall we get started? Does anyone currently here have any questions?
kevin.harrelson Did you shave this year for St. Baldrick's?
Shulie Tornel Questions for Matt can go here: https://docs.google.com/spreadsheets/d/13FvkrHwB7J1SAaQ_DPHPR4GszRTAtCUoA-5rf4jZPmw/edit#gid=0
Shulie Tornel If chat is laggy, please just click refresh!
Matt Martin I'll start by introducing myself. My name is Matt Martin, and I work in Keysight's ASIC design group. I do physical design for digital and mixed ASICs.
Matt Martin am also joined by Daneil Bogdanoff, who works in the oscilloscope division, and can help answer some of the more oscilloscope specific questions, as opposed to ASIC questions
Shulie Tornel Welcome @Matt Martin Thanks for participating!
Paul Stoffregen any chance for hints about future keysight products?
Daniel Bogdanoff Haha, paul, not the place for that :)
Matt Martin And to answer Kevin's question about St. Baldricks, my profile picture is only a few days old. But, I will be making a donation in the future when my hair is long enough.
pop13 Did keysight made the 1000x series intentionally hackable?
Matt Martin OK, so starting from the spreadsheet, I think Dave's question "How much is the cost of one ASIC in quantity one?" is a good place to start
Matt Martin And the answer is... A LOT
Daniel Bogdanoff It's easily millions of dollars
Daniel Bogdanoff but older processes can be cheaper
pop13 Ia m not thinking when it was still in dev state but like RIGHT NOW
Matt Martin So, the way ASICs are manufactured involves a large up front cost in engineering design. Once that design is complete, the foundry takes it and makes a mask set for photolithography. These masks are used to process wafers of silicon, yeilding tens to hundreds of die per wafer
Matt Martin So, it's hard to get just a single die
Matt Martin The actual cost per die depends on the process node the design is done in and the size and yield of the die
Matt Martin Some smaller signal conditioning ASICs are <$10 for a packaged and tested part
Matt Martin Big DSP chips can run into the hundreds of dollars
pop13 I ment the megazoom ASICs (if you can talk about it)
Paul Stoffregen Is all the scope's buffer memory actually on the asic die? I have a 4000x scope and I've used others from time to time and it's just amazing how much more responsive yours is.
kevin.harrelson Matt: I can field the MegaZoom question if you want... If I am allowed.
Matt Martin This is also a good lead in to 6th question "Any reasons to have separate linked dies, or is it more common to be etched onto the same silicon?"
Daniel BogdanoffThe cost of the specific ASICs is proprietary, but's it's definiltey more than a few bucks
Matt Martin Different process nodes have different performance characteristics
Daniel BogdanoffAnd the memory is built into the ASIC itself, which is why the scopes are so response
Daniel Bogdanoff responsive
Matt Martin Which also leads explains question 7 "Where are ASICS primarily used in scopes today? Is it mostly for high speed sampling, logic analyzer portions that are increasingly being incorporated? Mixed signal or mostly digital?"
pop13 So for the PCB guys its easy, just whack the ASIC down on the board, no external RAM etc.
Daniel Bogdanoff That's a big reason we use asics in our scopes because we can tune the hardware to be efficient for the specific processing tasksi
Daniel Bogdanoff instead of using an off-the-shelf processor
Matt Martin The basic block diagram for a scope has a signal conditioning front end, sending an analog signal into an ADC, which then ships digital data to a DSP/memory chip
Daniel Bogdanoff It's also not a freebie for the PCB team, though, ASICs are sensitive
Daniel Bogdanoff Can you briefly discuss the advantages of using a ASIC rather than an off the shelf ADC+FPGA, as are commonly used in low end scopes?
Matt Martin For the big digital chips, more advanced process nodes (meaning smaller transistor geometries) allow us to incorporate more logic and therefore...
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