ASIC #HackChat Transcript

A event log for ASIC Design Hack Chat

Let's talk mixed signal ASIC design for Oscilloscopes!

shulie-tornelShulie Tornel 03/17/2017 at 19:510 Comments

Matt Martin Shall we get started? Does anyone currently here have any questions?

kevin.harrelson Did you shave this year for St. Baldrick's?

Shulie Tornel Questions for Matt can go here:

Shulie Tornel If chat is laggy, please just click refresh!

Matt Martin I'll start by introducing myself. My name is Matt Martin, and I work in Keysight's ASIC design group. I do physical design for digital and mixed ASICs.

Matt Martin am also joined by Daneil Bogdanoff, who works in the oscilloscope division, and can help answer some of the more oscilloscope specific questions, as opposed to ASIC questions

Shulie Tornel Welcome @Matt Martin Thanks for participating!

Paul Stoffregen any chance for hints about future keysight products?

Daniel Bogdanoff Haha, paul, not the place for that :)

Matt Martin And to answer Kevin's question about St. Baldricks, my profile picture is only a few days old. But, I will be making a donation in the future when my hair is long enough.

pop13 Did keysight made the 1000x series intentionally hackable?

Matt Martin OK, so starting from the spreadsheet, I think Dave's question "How much is the cost of one ASIC in quantity one?" is a good place to start

Matt Martin And the answer is... A LOT

pop13 :D

Daniel Bogdanoff It's easily millions of dollars

Daniel Bogdanoff but older processes can be cheaper

pop13 Ia m not thinking when it was still in dev state but like RIGHT NOW

Matt Martin So, the way ASICs are manufactured involves a large up front cost in engineering design. Once that design is complete, the foundry takes it and makes a mask set for photolithography. These masks are used to process wafers of silicon, yeilding tens to hundreds of die per wafer

Matt Martin So, it's hard to get just a single die

Matt Martin The actual cost per die depends on the process node the design is done in and the size and yield of the die

Matt Martin Some smaller signal conditioning ASICs are <$10 for a packaged and tested part

Matt Martin Big DSP chips can run into the hundreds of dollars

pop13 I ment the megazoom ASICs (if you can talk about it)

Paul Stoffregen Is all the scope's buffer memory actually on the asic die? I have a 4000x scope and I've used others from time to time and it's just amazing how much more responsive yours is.

kevin.harrelson Matt: I can field the MegaZoom question if you want... If I am allowed.

Matt Martin This is also a good lead in to 6th question "Any reasons to have separate linked dies, or is it more common to be etched onto the same silicon?"

Daniel BogdanoffThe cost of the specific ASICs is proprietary, but's it's definiltey more than a few bucks

Matt Martin Different process nodes have different performance characteristics

Daniel BogdanoffAnd the memory is built into the ASIC itself, which is why the scopes are so response

Daniel Bogdanoff responsive

Matt Martin Which also leads explains question 7 "Where are ASICS primarily used in scopes today? Is it mostly for high speed sampling, logic analyzer portions that are increasingly being incorporated? Mixed signal or mostly digital?"

pop13 So for the PCB guys its easy, just whack the ASIC down on the board, no external RAM etc.

Daniel Bogdanoff That's a big reason we use asics in our scopes because we can tune the hardware to be efficient for the specific processing tasksi

Daniel Bogdanoff instead of using an off-the-shelf processor

Matt Martin The basic block diagram for a scope has a signal conditioning front end, sending an analog signal into an ADC, which then ships digital data to a DSP/memory chip

Daniel Bogdanoff It's also not a freebie for the PCB team, though, ASICs are sensitive

Daniel Bogdanoff Can you briefly discuss the advantages of using a ASIC rather than an off the shelf ADC+FPGA, as are commonly used in low end scopes?

Matt Martin For the big digital chips, more advanced process nodes (meaning smaller transistor geometries) allow us to incorporate more logic and therefore more functionality

Daniel Bogdanoff here's my thoughts

Paul Stoffregen is the fairly low resolution of the waveform display (approx 640 pixels) hard-wired into the asic design?

Matt Martin Whereas for the signal conditioning, a smaller degree of integration is needed, but we may benefit from higher performance transistors

Daniel Bogdanoff We get a lot more power out of using an ASIC without having to sacrafice performance

Daniel Bogdanoff Things like measurements, plotting, decoding are much more efficient in a dedicated ASIC

Daniel Bogdanoff Yes, paul, the plotting is hardwired, but the resolution is fairly on par with the other vendors

Paul Stoffregen yeah, so far nobody make a good high res scope

Daniel Bogdanoff @pop13, we won't be discussing future roadmap stuff

pop13 OK

Matt Martin So, these different requirements lead to multiple die - but the goal is to consolidate into as few ASICs as possible for the best price and performance

Matt MartinAnd I suppose, this answers question 3, as well: "How the heck do you achieve oscilloscope sample rates of 100Gsamples/s and higher?? Can you give a top-level description of the system? None of the engineers at my company know the answer to this :)"

Benchoff Hey everyone: I've been told to put this here. It's a spreadsheet of questions for the hack chat:

Matt Martin The answer is that there is a lot of secret sauce under the hood

Paul Stoffregen I use my 4000x scope quite a lot and it's by far the best scope I've ever used... and I have used many others. But the low res 12 inch screen with only 4M buffer sits next to my PC with a 4K 42 inch screen and nearly limitless memory

Matt Martin However, we have put a lot of effort into intgerating as much functionality into a few key ASICs as possible

Daniel Bogdanoff Yes, Paul, think about how every single point has to get majorly processed

Evan Juras @Matt Martin what techniques do you use to get such high analog bandwidth in your ASICs?

Paul Stoffregen is a higher res scope with this level of performance simply beyond what today's asic technology can deliver?

Daniel Bogdanoff at really high rates

Matt Martin Thus, if you open up one of our scopes and one of our competitors scopes, you will see far fewer discrete components. This integration leads to much better signal integrity

Bil Herd @Benchoff Brian didn't you mention a low cost low run ASIC foundry once, like $200-300K?

Matt Martin And therefore, better performance

Daniel Bogdanoff There's always a trade off, Paul. A "4k" scope is certainly possible, but it would mean sacrificing a lot of important design specs

Daniel Bogdanoff We encourage people to scale their acquisitions to help make up for that

Daniel Bogdanoff But things like waveforms per second and price of the scope

Daniel Bogdanoff and scope's chip

Matt Martin Here's another good question:: "Along with new299's question -- how do you decide when to give up the FPGA and go for the ASIC? What kind of questions should I be asking myself?"

Matt Martin FPGAs are wonderful tools

Matt Martin They are great for prototyping, and are often a low cost alternative to an ASIC

pop13 Why should i choose the Keysight 1000x series than a 4channel scope with the same bandwith (both the lowest end of the series)?

Matt Martin The decision to move to an ASIC ultimately boils down to performance. FPGAs have limited internal resources. So, for example, putting the acquisition memory in the scope chip gives us a huge performance boost, and the FPGA that has as much memory as we need just doesn't exist

Daniel Bogdanoff For the 1000X, one of the things I love about it is the reliability and responsiveness, but that's hard to quantify in a Data Sheet.

Daniel Bogdanoff We''ve seen that many people really only use two channels, and have a bunch of un-opened probes sitting around

Matt Martin For general data processing, you can also get higher performace because you have dedicated circuitryM

Paul Stoffregen agreed - if you actually use a rigol and a keysight for actual troubleshooting, the performance difference is incredible.

Matt Martin internal logic gate and route is optimized

Daniel Bogdanoff You also get the +1 digital channel,which is nice for some quick checks of clocks, etc.

pop13 But my use for a scope is in the middle of analogy and digital stuff, how do you decode a full blown SPI bus with two channels.

Matt Martin You don't have to be shoehorned in to the FPGA's architecture, where you may get scenic routing, less than perfectly optimal logic gates, etc.

Daniel Bogdanoff You can do 3-wire spi using the "trigger in" B

MobileWill @pop13 This may help

Daniel Bogdanoff But there are times when you simply need 4 channels

Kevin I was working on a project recently where a four channel scope would have been handy. I only have 2 channels on my current scope. I could use two 2-channel scopes but I only have the one. Sometimes you need more than 2.

Daniel Bogdanoff For all tools, you have to look at what you need to do and go from there

pop13 thx, and thats the problem the 2000x series is expensive, mut the 1000x has only two channels, so i think i stay with the cheap rigols, sorry keysight

Matt Martin On to question 25 "What tools do you use for design,simulation and layout?"

Kevin I needed 3-channels to more easily do what I was trying to do.

Daniel Bogdanoff We definitely know that the 1000X isn't the tool for every job, but for a lot of engineers it will be just what the Dr ordered

Paul Stoffregen @pop13 - you really should try actually using both scopes!

Matt Martin And the answer is "Lots of them!"

Matt Martin There are the "Big 3" vendors of ASIC EDA (Electronic Design Automation) software: Cadence, Mentor, and Synopsys

Matt Martin We use tools from all three, plus several smaller vendors

pop13 Man, i need to move out more, i need to go to more trade shows and try more scopes out. @Paul Stoffregen

Matt Martin For analog design, schematic capture and layout is done within Cadence's Virtuoso suite of tools

Kevin Interesting. With FPGA's we would typically use tools provided by the FPGA vendor. When it comes to ASIC's you can more easily use third party tools?

0xcaffee Hello

pop13 hello

0xcaffee I came here to participate in the Q&A thing. How does this place work?

Matt MartinFor digital, RTL is written in the text editor of choice, then passed through a synthesis tool to turn into gates

Paul Stoffregen or maybe Keysight needs to move in more, get folks at hackerspaces more hands-on experience with their products?

Matt Martin We tend to use Synopsys's design compiler for that

Paul Stoffregen or maybe Keysight needs to move in more, get folks at hackerspaces more hands-on experience with their products?

Matt Martin Digital placement, routing timing closure is in Cadence's Innovus tool

Daniel Bogdanoff FYI, we both have to run out at 12:40 PST. If you have more questions,

Neil Cherry @0xcaffee, ask question, get answer. What we don' know, we make up ;-)

0xcaffee Anyway, I have been self-learning verilog for quite some time now, and I have been wondering, when should one go beyond RTL spec?

Daniel Bogdanoff Check out our YouTube channel:

Matt Martin And then physical verification is in Mentor's Calibre suite

pop13 @Paul Stoffregen Thats true, if you can try the scope than you will be like, man this is great i save up for it.

Daniel Bogdanoff We have a livecast coming on Monday where I'll be doing some live QA. You can also hit me up on Twitter

Benchoff @Oxcaffee: here's a spreadsheet with the questions. Add one:

Matt Martin Simulation we use a variety of vendors, depending on designer preference

Bil Herd Heh, I know some shops where there is an engineer whose main function is to keep all of the scripts running that make the tools work with each other.

Daniel Bogdanoff And, we're giving away free oscilloscopes in March! Check out

pop13 The sad thing about the scopemonth that slovakia is on the list :(

Matt Martin And Bil, we do a lot of that. While the vendors provide the tools, we write our own scripts to drive them

kevin.harrelson Daniel: Can you give a scope away to everybody on this chat????

pop13 :D

Daniel Bogdanoff Haha, no Kevin :) I wish I could!

Bil Herd TCL and the like?

0xcaffee Okay Benchoff, figured it out

Matt Martin One of the things I really like about working for Keysight is that I can be involved in that process. We are small enough that there is not a golden methodology handed down from on on high that I as a desicner cannot alter

Paul Stoffregen that sounds very much like how I did a student project asic in the early 90s.... Mentor tools and lots of scripts to actually do things.

Shulie Tornel Any more last questions or last announcements?

0xcaffee Well, I added a question to the spread sheet thing

Matt Martin But yes, lots of TCL and makefiles

0xcaffee Col35

Daniel Bogdanoff Yes, there are easter eggs, but if I told you where they were that'd be no fun :)

Dajgoro Labinac "there is not a golden methodology handed down" oh, i thought such companies were all always strict on their way of doing things

Daniel Bogdanoff I'd encourage everyone to go check out the Keysight Oscilloscopes YouTube channel and sign up for scope month!

pop13 Alexa, tell me how to trigger the easter eggs in keysight scopes.

Daniel Bogdanoff For easter eggs, check out the EEVBlog forum, do a quick search for it. Most have been found

Matt Martin And many companies are. Being a relatively small ASIC design shop, we are free to innovate more

Shulie Tornel Cool!

Daniel Bogdanoff It varies from scope to scope, but for InfiniiVIsion scopes, setting the screensaver text to "TREK" brings up a hidden saver

Daniel Bogdanoff there's also minigolf and etcha-a-scope

Daniel Bogdanoff and duck hunt

Kevin O' Brien I'll have to get searching for those Easter Eggs. Passed many an hour playing tetris and caterpillar on old HP scopes. Ready to switch back to an interesting looking waveform should a manager walk in. Luckily, they were rarely to be seen in a lab.

Matt Martin And with that... I think it is time to be goingThank

Matt Martin the questions, and I hope this was informative

Jørgen Kragh Jakobsen How big is your Asic design group

Kevin Oh, nuts. I forgot to enter scopemonth yesterday and haven't done it yet today. thanks for the reminder, pop13

Kevin O' Brien Great to see that Keysight haven't lost or discouraged that kind of expression from their engineers.

0xcaffee hah, I see I came in too late

Daniel Bogdanoff We're out of time, thanks for all the questions!

pop13 You know, if you want a maximum productivity lab dont buy agilent gear, you guys put an easter egg on a function generator.

new thanks! It was interesting!

Shulie Tornel Thank you so much @Matt Martin and @Daniel Bogdanoff!!

Paul Stoffregen thanks for ;)

Bil Herd Thanks guys!

Dajgoro Labinac bye

pop13 Bye @Daniel Bogdanoff , @Matt Martin

0xcaffee However, I guess there is at least one person in this place who can help me figure this out ;>

Daniel Bogdanoff Adios! 👍

Luke Does anyone have a way to get the hack chat in some sort of lighterplatform? This web chat system brings my computer to it's knees.