Electronic Engineer

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This user joined on 12/30/2014.

Things I've Built

Channel 7 Sydney

Very Long sign Spanning 3 sides of the building, the 200mm character height display has a total length of 140 metres (70 in both red and white LED’s), which equates to approximately 383 characters per line.

Keno LED Sign

LED Sign to display keno numbers.

Upper House

LED Sign project, had animated arrow pointing up. Also animated arrow down for Lower House.

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Michael Gardi wrote 02/16/2022 at 08:44 point

Thank you for your interest in my WDC-1 a "Working Digital Computer" project. 

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Samuel A. Falvo II wrote 12/20/2021 at 05:50 point

Thank you for liking the Kestrel Computer Project.

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Igor wrote 10/07/2021 at 11:22 point

Thank you for liking my #CRISS CP/M 8-bit Homebrew DIY Computer (AVR based) ! Computer is getting closer to standards: in new fw versions it supports VT100/ANSI terminal and learned sleep mode :)

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Michael Gardi wrote 09/16/2021 at 13:40 point

Thank you for liking and following my Sol-20 Reproduction project.

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Ken Yap wrote 01/21/2021 at 15:55 point

Thanks for following #8085 Minimax 
But please note that this project is shelved, and anyway the design is not mine. The circuit has been verified as viable by other people. So nothing to see here.

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roelh wrote 06/18/2020 at 13:00 point

Hi, thanks for liking #VGA generation card !

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Thomas wrote 01/01/2020 at 08:31 point

Hi - thanks for liking my little lazy MODBUS with Forth project!
By the way: Happy New Year :-)

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Laser Developer wrote 02/08/2019 at 05:15 point

Thank you for liking and following Open Source LiDAR - Unruly! Comments and suggestions are most welcome :). LD.

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Ed S wrote 10/28/2017 at 11:16 point

Thanks for liking our #OPC-5 - a CPU for FPGA, in one page project!

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prof_braino wrote 12/30/2014 at 20:52 point

Thanks! We are preparing to release PropForth 6 shortly. PF6 will support using the prop cogs as a "multitasking pool" for more than 8 tasks (up to memory limit) with a small overhead cost. Also, PF6 will begin FPGA support. We can now tweak the propeller cpu itself, removing unused resorces, optimizing for FORTH execution, and adding "hardware" (ADC/DAC, etc) in FPGA. May be interesting and possibly useful.

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