joan lluch


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joan lluch wrote 08/24/2019 at 22:08 point

Hi roelh, no problem. I'm very interested on your work. I find it fascinating. I am on the way to make a 16-bit TTL Risc computer. So far I'm posting my progress here and here but I'm mostly a software guy, so only by reading your posts I have already learned a lot. So far I defined the ISA and made a LLVM based Compiler, an Assembler and a Simulator, but no hardware yet!. I may contact you in the future for some questions about your Kobolt computer if you are available. 

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roelh wrote 08/25/2019 at 09:53 point

Hi Joan,

also thanks for liking my other projects ! Sure you can contact me for questions. I've read your anycpu-thread. Since you want to built a RISC device, my RISC Relay cpu might give you more inspiration than Kobold, since Kobold is very CISC, depending on microcode, while the RISC relay cpu does everything in one cycle. The RISC relay cpu has got a bit complicated, mainly because it supports BCD as well as binary arithmetic, and 16x16 multiply with only 16 consecutive instructions. But this complexity can be stripped off.

I've seen your instruction set V7, and I'm afraid you will have a hard time decoding all those 7 instruction formats in hardware. If you want, I can help you simplify this.

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joan lluch wrote 08/25/2019 at 16:03 point

Hi roelh, I found your relay cpu some time ago and I had a pleasant read about it. I must say that before I decided to attempt a TTL computer, I wanted to make a relay based one, so I performed some internet research on relay computers too. I regard yours as one of the most interesting ones, if not the best!. 

I will be interested, when the right time comes, to learn about the Kobold Video interface. So far I'm an amateur on hardware design beyond the very basics, so everything I read on the subject is very new to me.

About my cpu74 instruction set and encodings, I have put a lot of thought on it. I understand what you say, and of course I am open to suggestions. The main issue here is that it's not possible to have a more regular encoding if I want to keep large embedded immediate fields and 3 operand instructions, unless I reduce significantly the total number of instructions.  But I could have missed something...

The decoding (of the current set), can be performed by inputing the 10 most significant bits of the instruction into one or more PLAs which will generate the control bits by looking only at the relevant encoding bits.

Alternatively, and more preferably, the instruction encoding bits can be converted into unique 7 bit opcodes by means of a relatively simple set of logic gates. These the (7 bit) opcodes can be input into a smaller PLA or just an EPROM to create the control bits in the usual way. Note that register operands, condition codes and immediate fields can be easily decoded separately because they are always in the same places.  That's my idea on how to do it, but of course, other approaches are greatly appreciated.

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roelh wrote 08/25/2019 at 20:05 point

Hi Joan, you can have a look at this instruction set that could give you inspiration, providing facilities that I also see in your instruction set:

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roelh wrote 10/27/2019 at 13:42 point

And thanks for following #RISC Relay CPU !

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joan lluch wrote 11/16/2019 at 18:42 point

Hi roelh, I posted a question on your RISC relay cpu project.

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roelh wrote 08/24/2019 at 20:31 point

Hi Joan, thanks for liking and following #Kobold - retro TTL computer  !

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