This format mirrors DI, only difference is both operands are register.
Opcode | Mnemonic | Description | Flags |
0b0000 | AND(B) reg1, reg2 | Logical conjunction | P, Z |
0b0001 | OR(B) reg1, reg2 | Logical disjunction | P, Z |
0b0010 | XOR(B) reg1, reg2 | Exclusive OR | P, Z |
0b0011 | BRS(B) reg1, reg2 | Reset those bits of reg1 set in reg2 |
P, Z |
0b0100 | ADD(B) reg1, reg2 | reg1 ← reg1 + reg2 | P, N, Z, V, C |
0b0101 | ADC(B) reg1, reg2 | reg1 ← reg1 + reg2 + C | P, N, Z, V, C |
0b0110 | SUB(B) reg1, reg2 | reg1 ← reg1 - reg2 | P, N, Z, V, C |
0b0111 | SBC(B) reg1, reg2 | reg1 ← reg1 – reg2 - C | P, N, Z, V, C |
0b1100 | CMP(B) reg1, reg2 | Set flags like SUB(B), discards the result | P, N, Z, V, C |
0b1110 | LD reg1, reg2 | Loads reg1 from reg2 | no effect |
0b1111 | ST reg1, reg2 | Stores reg1 to reg2 | no effect |
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