Please share ideas for an integer clock divider with excellent phase preservation

Simon Merrett wrote 04/26/2022 at 09:46 -1 point

I'm trying to divide eg single digit MHz clock by an almost arbitrary (non-power-of-2) integer and convert it to logic level pulses in the range of around 1-100 Hz. I'd like to minimise the phase lag of the rising pulse with respect to the input signal. I can condition the output signal for a faster rise time if needed but I estimate the edge needs to be launching within around 1 to 10 nanoseconds of the trigger edge arriving. 

I have heard of people hand coding assembly on a PIC and feeding the reference clock into the PIC's clock input to achieve something similar but does anyone know of a good guide, specialist parts or particular IC / microcontroller peripherals that are designed to do this?