I've been doing some experiments with this recently. I haven't tried it with etching, but I've had a bit of success with milling in FR-1. I used an Othermill with a 0.006 inch 2-flute flat endmill and toolpaths generated with FlatCAM. (0.006 inch is the smallest mill I've been able to use reliably without constant breaking.) I did it for an iCE40 UltraLite FPGA in a WLCSP-16 package (4x4 ball grid). Routing the inner 4 balls is a problem, of course. The pinout of my device is such that they can't be left unrouted - 3 of the pins are required for (1) power supply and bitstream programming (2). However, I have been able to route them via the outer balls (i.e. short the pad for an inner ball to an adjacent outer ball). The outer balls are IO pins that, at power up, are very weakly pulled up (approx. 100kOhm). When the chip enters programming mode, it then tristates the IO pins, and I program the device with bitstreams that leave the IO pins in question tristated. The problem with my footprint is that I loose 4 of the 10 IO's on the device (the 3 outer pins I routed across, and the one inner pin that I do not route). I'm currently experimenting with other methods to remedy this, and allow all the pins to be routed. If you're interested, I could create a project page to share my work thus far.