This isn't an original idea - I have found similar notions dating back to at least 1952!
Anyway, the idea is to make a DRAM memory cell with just a capacitor and two diodes. I played with one back in 2009, and am documenting it here briefly since there seems to be some interest in these things. I never made it fully operational with decoded address lines, but was able to verify storage of a few 4-bit words with transistor sense amps and LEDs. Here's the unit (glad I dated it!!):
Here is the schematic:
There are two diodes and a capacitor in each cell. The diodes connect to two individual lines per column - a "write 1" line and and a "write 0" line. To write a 1 to the cell, the appropriate row line is grounded, then a positive voltage is applied to the appropriate "write 1" column line. Current flows through the one diode to charge the cap. To write a zero, the row line is grounded, and so is the appropriate "write 0" column line. Current flows through the other diode to discharge the cap. Reading also uses the "write 0" line - any time the row line is grounded, current flows from the cap to the sense amplifiers.
Like any DRAM, this needs to be periodically refreshed. My original intent was to use this idea for the RAM of a diode-only computer, but I could not get diode-only sense amps sensitive enough, so I shelved the idea. In the intervening years, I figured out the diode amplification problem, but never got back to the memory idea.
I was always a little worried about somehow reverse-biasing the electrolytic caps in this circuit, but I'm pretty sure I convinced myself that it was OK. It has been a while.
I was a little surprised I still had this thing. I save way too much crap.