I2C looks simple because it needs only two signal lines. The simplicity is deceptive. SDA and SCL are open-drain buses, so the pull-up resistors, trace capacitance, device count, cable length, and voltage levels all determine whether the edges are fast enough and whether the bus can sink the required current.

Why the resistor is a timing component

When a device releases the line, the pull-up resistor charges the total bus capacitance. The rising edge is approximately RC behavior, so a smaller resistor gives a faster edge and a larger resistor gives a slower edge. But a smaller resistor also increases the current every time a device pulls the line low.

The bus capacitance includes pins, package parasitics, traces, connectors, level shifters, and cables. A value that works on a short breakout board may fail when the same sensor is moved to a remote enclosure.

Check both limits

The pull-up must be small enough for the required rise time and large enough that the sink device can pull the line below its low-level voltage. A simplified low-level current is:

IOL ≈ VDD / Rpullup

Compare that current with the device’s specified sink capability, including voltage drop and temperature. The fastest possible bus is not useful if the sensor cannot pull the line low reliably.

For a first estimate, calculate the bus capacitance and use the relevant I2C rise-time requirement. Then validate with a scope at the farthest device, not directly at the controller pins.

Watch for duplicate pull-ups

Every breakout board may include its own pull-ups. Three modules can quietly put three resistor pairs in parallel. The effective resistance becomes lower, the low-level current rises, and the bus may work at one voltage while violating another device’s limits.

Before debugging software, inspect every board and module in the chain. Record which pull-ups are installed, which voltage they connect to, and whether they can be removed or switched.

Level shifting changes the topology

An I2C level shifter is not just a pair of voltage dividers. Bidirectional open-drain translation depends on the device topology, pull-up placement, edge rate, and bus capacitance on both sides. Put the pull-ups at the correct voltage domains and check whether the shifter adds leakage or delay.

The voltage-divider calculator at ResiCalc is useful for understanding why a resistor divider is not a drop-in replacement for a bidirectional open-drain level shifter. The correct network depends on the electrical behavior of the interface.

Layout still matters at modest speed

Keep SDA and SCL away from high di/dt switch nodes and motor traces. Provide a continuous reference path and avoid long stubs. If the bus leaves the board, consider connector pin assignment, ground adjacency, cable shielding, and transient protection.

For a dense mixed-signal board, MOZPCB’s controlled-impedance PCB guidance is a useful reminder that trace geometry and return paths affect signal behavior even when the bus clock is not especially fast. The goal is not to force every I2C route into a high-speed design rule; it is to keep the physical path predictable.

A practical bench sequence

1. Start with one controller and one target on the shortest connection.
2. Capture the rising and falling edges at the target pins.
3. Add modules and check the total pull-up resistance after each step.
4. Increase cable length and repeat at minimum and maximum supply voltage.
5. Test clock stretching, repeated starts, bus recovery, and power-up sequencing.

If the bus fails only when another subsystem turns on, inspect shared ground impedance and supply noise. A ceramic-capacitor selection guide can help when choosing local bypass parts for the controller, sensor, or level shifter.

Octatronics’ technical resources provide useful application context for sensor, communications, and industrial designs. I2C reliability comes from treating the “two simple wires” as a complete analog and digital system.