So, the PCB Gremlins got to the TritiLED V3.0 board. The timestamp on the gerber files is at 20:49 local time, making me think that the mysterious PCB-bug-inducing behavior is not limited to post-midnight design sessions.
I ordered the boards before prototyping the circuit: today, on a breadboard, I found the problem - an input line on the 74LVC1G123 pulled high when it should be pulled low. I haven't even received the PCBs back yet. I can rework the three incorrect PCBs easy enough - cut a trace and run a piece of wire-wrap - but it means another order to have a "releasable" version for the coin cell challenge.
Moral of the story: even the relatively early 20:49 is late enough for the PCB Gremlins to strike.