I'm starting a project page! I'll hook it all together this afternoon. https://hackaday.io/project/164349-yayaz80

In general, problem with Motorola bus specs is that Their chips treat R/W line as sort of an address line. It is supposed to be set and stabilized in advance of actual data access. The reasoning behind this is to prepare internal bidirectional bus drivers to assume proper direction for the data in advance of the data bus transfer.

On the other hand, in Intel/Zilog bus, there are separate /WR and /RD control signals, and basically if /RD is high, no chip should drive data bus.

Now, Motorola chips won't drive data bus either, until they are selected while R/W is high.

On write cycle, minimum duration of CS for slowest M6810 variant is 300ns (by the specs), and Z80 turns its /WR signal low for the duration of one clock cycle, from middle of T2 till middle of T3, so max. Z80 CPU clock frequency for M6810 is 1/300ns = 3.33 MHz. If you have M68A10, you can run your CPU at full 4MHz, and with M68B10 you could go up till whooping 4.76 MHz. However, I understand that you want to single-step the computer manually, so this will probably not matter.

For interfacing, IMHO it would be safe to

1) attach inverted Zilog's /RD signal  (let's call it e.g. RD) to R/W line, so that it is positive only during read cycles, and

2a) make one of M6810 positive CS lines as /RD NAND /WR (high when either /RD is low or /WR is low) , or alternately

2b) make a negative /CS line as /RD AND /WR (low when either /RD is low or /WR is low),

3) connect one M6810 /CS line to Z80 /MEMRQ line, and

4) the rest of CSs and /CSs you can use for additional address lines from upper address byte to achieve your multiple chip banking.

Since CSs are more scarce than /CSs, if you use 2b instead of 2a, you will have a more balanced mix of free CSs and /CSs. On the other hand, you will probably use up one of the remaining /CSs anyway by most likely using an 74HC138 or 74HC139 decoder for address decoding. Those decoders have negative outputs, a good match for one of /CSs, so either way you'll end up either with an odd CS or with an odd /CS.

Mind the power consumption (it's an NMOS chip and a single one draws up to 100mA at 5V) and fanout of your control circuitry outputs. I mean, don't get crazy with the RAM chips, they drink like camels.

Good luck!

The _WR line goes to the R/_W  while the _RD lines goes to the _OE on the RAM.  The rest of the chip selects are for enabling the RAM

I forgot the OE signal. I knew there was something missing :)

Looking at the bus cycle specs in the Mostek Z80 data sheet, and they show somewhat more than 1 clock cycle for an access, but it is less than 1.5 clock cycles.

It looks like the ~mreq signal on the Z80 needs to go into the address decode logic to separate memory accesses and I/O accesses.

The 6810 has 6 chip select inputs, so it can do some of it's own address decoding.

CS0  active high

CS1   active low

CS2  active low

CS3  active high

CS4  active low

CS5  active low

If you do your own external address decoding, you would tie the Z80 ~Write Enable signal to the 6810 R/~W input, and tie all but one of the above mentioned chip selects to their active state. The output of your chip select logic would go into the remaining chip select input on the 6810.  I am not sure about the timing on the bus cycles, that would take a lot more digging.

The 6810 is a tiny RAM by the way (128 bytes).
There were lots of 2K Byte and larger SRAMS around in the Z80 days.

Thanks! I'll try it out tomorrow!

Also, the reason I'm using a 6810 is because it was the only SRAM I had on hand.

The 6810 was availible in 1MHz, 1.5MHz and 2MHz speeds. Looking at the Mostek data sheet, I suspect that you will run into timing problems if you try to run the Z80 faster than the frequency rating on the 6810. It looks like the Z80 bus cycles are only 1 clock period long. So a 2MHz 6810 should work if you don't clock the Z80 faster than 2MHz.

Bharbour, I'm planning on running the z80 via a manual clock. I'm sort on parts so I'm using an arduino to drive most of the stuff, I just want a smige of ram to play around in.

 @Bharbour  The Z80 takes mltiple cycles for memory access, so you have to take that into account.

i.e.  don't just equate the 6810 frequency to the clock Z80.  Read the parameters and the math.

A search found this as a first hit: https://www.datasheet.live/index.php?title=Special:PdfViewer&url=https%3A%2F%2Fpdf.datasheet.live%2Fe2d22a53%2Ffreescale.com%2FMCM6810CP.pdf

The Z80 lines are actually active low, hence written with a bar on top. If you look at Grant Searle's Z80 MCU design http://searle.hostei.com/grant/z80/SimpleZ80.html#CircuitDiagram , you can see the OR gates used to generate /MEMWR and /MEMRD signals whcih then drive /WR and /OE of the SRAM. In your case your SRAM doesn't have /OE so you would use the /CS inputs. You need to connect /MEMWR to enable one /CS.

Why the 6810? Is that all you have in your parts box? Sure you can't manage a 2kB or 8kB SRAM chip?

Thanks! That clarifies a lot. I'll be posting updates as I continue. I think I'll make this a project.

I found a datasheet!

http://bitsavers.trailing-edge.com/components/motorola/_dataBooks/1984_Motorola_Memory_Data_Book.pdf

I still need some help.

Also, how could I hook it up to address multiple of the banks. I don't want to be restricted to only 128 bytes.

You would use an address decoder chip to select particular chips using the chip select inputs.

Oh god! How many of these 6810s do you have on hand?