Verilog equivalent for VHDL's concurrent "with .. select"-Statement

Mario wrote 11/20/2019 at 11:09 0 points

I was searching for the equivalent of the above stated statement in Verilog. Is it just the ternary operator? This was the only one I found.

Or do you always put them into an always block and use switch case? What's the best option here? I want to build a simple ALU and just made it like that:

assign o_y = (opc == 4'b0000) ? a & b :
                (opc == 4'b0001) ? a | b :
                (opc == 4'b0010) ? ~(a & b) :
                (opc == 4'b0011) ? ~(a | b) :
                (opc == 4'b0100) ? a ^ b :
                (opc == 4'b0101) ? ~(a ^ b) :
                (opc == 4'b0111) ? ~a :
                'h0000;

Is that a good solution?