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New VDC-II Core Might Replace CGIA Concept

A project log for Kestrel Computer Project

The Kestrel project is all about freedom of computing and the freedom of learning using a completely open hardware and software design.

Samuel A. Falvo IISamuel A. Falvo II 03/26/2020 at 17:340 Comments

Followers know that I've pivoted this project several times.  And I'm sure I'll pivot several times more in the future before I am satisfied with the outcome.  This post is to announce my most recent pivot.

To help factor the project down into more manageable chunks, I've been convinced by others (and I agreed) to target the RC2014 backplane standard; specifically the RC80 variation, with a CPU card and one or more supporting I/O cards.  However, I need to get my feet wet with designing FPGA logic that couples with a 7.3728MHz, 5V bus that speaks the Z80 protocol first.  Therefore, before I decided to not start with the CPU card, but rather, with some manner of I/O card.  I already completed the MGIA core for the Kestrel-2 family, so I figured this would be a good option to get working first.

There are some problems that I needed to resolve first though, like how to access video memory and so forth.  The TMS9918A uses an indirect approach for this, but so does another chip which seemed closer to my immediate needs: the Commodore CSG 8563 and 8568 VDC chips.  As I was studying the Commodore 128 Programmer's Reference Guide, I noticed this chip has a fair bit of similarity with what I'd originally hoped to see in the CGIA core as well.  Not only that; but, the HBIOS software on my RC2014 has a CSG 8563 driver in its source tree already, so a motivated developer can have a much easier time porting the system software.  Creating a VDC variant seemed to be the logical choice.

So, I've decided to make a small diversion and focus my development efforts on building a project with a reasonable successor to this chip, which I've dubbed the VDC-II core.  To minimize costs and as many risks as I can, I've decided to build the prototype of the core in a TinyFPGA BX module.  Although far more resource limited than the icoBoard Gamma, it does at least have 16KB of block RAM inside it, which is enough for an 80-column text display with 16 colors, or a 640x200 monochrome bitmapped display, which is a good match for what the Kestrel-2's MGIA core can already do, and what CP/M software reasonably expects.  I suspect I'll be able to reuse much of what I'd already written for the MGIA.

I want to see the VDC-II core to completion; if nothing else, once the basic core is working, I think I can expand upon it in ways similar to how the V9958 expands upon the TMS9918A.  If so, then perhaps the VDC-II and its successors can become the new video core for the Kestrel-3 (see?  I told you I was making progress on the Kestrel-3!).  I can also see this project as being something which I could perhaps sell one day on Tindie, CrowdSupply, or some similar outlet as an RC2014 board kit.

So, with that in mind, I think I'm going to document this project separately from the Kestrel-3 project.  Yes, it'll most likely end up as the Kestrel-3's video core; but it has wider applicability if I can drive it to completion.  I know my track record here isn't stellar.  But, I'm willing to at least try.  I see this challenge as practice for more ambitious goals in the future.




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