This is a wacky idea on which I have been working for some time, yet it is still in very early stage of development. The final goal is to make it as a reliable FPGA soft-core model, or even better - a small chip.
CPU7 is strange in many aspects.
First, it is a RPN (Reverse Polish Notation) system, and its native assembly language is somewhat similar to the Forth language with many high-level looking words such as IF, WHILE, LEN$, etc. It is natively 14-bit, but scales automatically up to 56-bit when needed.
Another interesting feature is the possibility to dynamically create or destroy virtual cores, each running independently as a system on its own. CPU7 creates them when needed, and then they disappear completely. This is equally valid in the cases where CPU7 runs a single hardware core, or many hardware cores. The scheduling is internal and completely transparent to the user.
The entire model is simple enough to be coded into a small FPGA.
Files
emulation.zip
Early alpha version of CPU7 emulation code written in C (probably buggy)
Although natively working with 16-bit words (14-bit pairs of instructions or data), CPU7 is also supposed to handle "raw" unformatted data in 8-bit, 16-bit, or 32-bit format. As an example that could be a hardware register, video memory, or anything which is not part of CPU7.
As a small coding exercise to test the flavour of the CPU7 assembler, here is the well known "bubble sort" of an area of unformatted bytes.
'! usage: addr len bubblesort8
:bubblesort8
dup 1 > if `! check if the arrayis more than one element
enter
1 over + `! calculate end=addr+len; stack: beg, end1 swap dup `! stack: end, beg, addr
repeat
dup rd8 `! stack: end, beg, addr, [addr]
1 over ++ rd8 `! stack: end, beg, addr, [addr], [addr+1]
< if `! stack: end, beg, addr
++ `! addr=addr+1else
dup rd8 `! stack: end, beg, addr, [addr]
1 over ++ rd8 `! stack: end, beg, addr, [addr], [addr+1]
2 over wr8 `! stack: end, beg, addr, [addr]
1 over ++ wr8 `! stack: end, beg, addr
drop dup `! addr=beg; stack: end, beg, addr
endif
dup 3 over < until
leave `! clean up the data stack
endif
drop drop `! remove the input parameters from the data stack
;
Thank you very much for this interesting project. I've implemented most instructions of cpu7 in Verilog https://github.com/wil-low/projf-explore/tree/main/cpu/cpu7 . It was fun!
Nice project. The choice on the 7 bit is interesting. I have created a homebrew CPU also using 7 bits of data, although mine is more minimalist and designed to support functional programming.
Thank you very much for this interesting project. I've implemented most instructions of cpu7 in Verilog https://github.com/wil-low/projf-explore/tree/main/cpu/cpu7 . It was fun!