Looking again at the full adder circuit, there are 3 SPDT relays (the DPDT relay counts as two SPDT)
The "critical datapath" goes through C, which has an inverter (implemented by the bottom relay). This means that C should be the input connected to the switches and not a carry input. Then the problem is to "regenerate" the Carry signal because the chain can be quite long and would overload one relay. So ideally the carry out goes to input B, while input A comes from the flip-flop.
(drawing To Be Drawn)