Someone asked how the LDC instruction works. The LDC is needed for the Harvard architecture, were the program memory is separated from the data memory. So when you have a table of constants in program memory, you can not use a normal memory instruction to get such a constant into your processor. That is why there is a special LDC (Load-Constant) instruction. 

The short version is this:

The LDC instruction uses the fact that the 12 bit program counter consists of two 12-bit wide latches. The first latch group is called the master PC, and the second latch is called slave-PC. The slave PC can be loaded with an incremented version of the master PC, and then the master PC can be loaded from the slave register to increment it. The slave PC also directly drives the address bus of the program memory.

Like most instructions, the LDC uses one of the address registers. In this case, the contents of the selected address register is loaded into the slave PC, while the actual PC value stays available in master PC. The address is now connected to the address bus of the program memory. In the next cycle, the contents of the program memory will not go to the instruction register (that will be cleared, and execute a NOP), but it will go to the DH register. Then, the slave PC is reloaded from the master PC (that still contains the programcounter value), and the next instruction will be executed as normal.

And now the detailed version:

The LDC is decoded on the Clock&Control pcb, by RL170 on the schematic. Normally, this relay is attracted but for the LDC instruction it is not. When the LDC is detected, this relay causes the following actions:

• The slave PC is not loaded from the master pc, because the PC_TO_SLAVE signal is blocked by RL170.
• The LDC_TO_SLAVE signal is activated in phase 3. This goes to the Program-counter PCB, where it cause that the signal group LDC_D0 to LDC_D5 is transfered into the slave register. This signal group comes from the 96 pole connector pin B9, C9, B15, C15, B17, C17. On the backplane this connects to REG_PB bus (register port B) that is connected to the selected address register. The first PC program counter board connects to the bits D0 - D5 and the second board connects to D6 - D11.
• RL170 also causes that relay RL171 (on schematic next to RL170) is set. This causes that in the next cycle, RL172 prevents loading the master PC from the slave PC, and the instruction register is not loaded. RL171 also activates the signal LDC_WR, going to pin A17 of its connector.  On the main board this connects to pin C10 of the lower program counter board. On the schematic of the PC, you see it on page 3 where it controls RL341. This relay will block the clearing of the master PC (because it does not get its incremented version from the slave PC, and it must keep the same value), it will clear the DH because that will get a new value, and it will generate the CODE_TO_DH activation signal. This will go to pin C29 of the connector, and over the main board to the PROG "Program memory and instruction register" board on pin A28. There it will, on page 2 of the schematic, connect the codeword (from the program memory) to the LINK bus. The LINK bus connects directly to the 16 bit DH register. (The same LINK bus is used to transfer the pc value to DH when a subroutine is called).