In this log I give some schematic info. I will explain the principles of the instruction decoder. (The ALU and registers are already discussed in one of the files).

In the HAD files section, the schematic RRC1613.pdf is a “summary” of the total design. There may be differences between the descriptions. It is hard to keep everything in sync as long as the design is not yet final.

Above the long line of RRC1613.pdf, you see the data path essentials for 1 bit (register and ALU). Below the line, the essentials of the instruction decoder are shown. The schematic is intented to give an overview of the polarities and pull-up/pull-down capabilities of the signals.

The clocking is not yet in the drawing. For every instruction there are four phases:

• 1) Called PH1 in schematic. Write to relays of register latch 1 group (CPU registers)
• 2) Write to relays of "Next state function 1"
• 3) Called PH3 in schematic. Write to relays of register 2 latch group (like the ALU input registers)
• 4) Write to relays of "Next state function 2", like the carry relays and logic result relays.

Phase 2 and 4 are not clocked, they are are direct result of the actions of phase 1 and 3.

At the lower left, you see the relays of the instruction register:

Y0 Y1 mode zpage/immediate/memory/register
A1 A0 addressregister / src register
R2 R1 R0 dst register
M2 M1 M0 operation code

The upper contacts of these relays are for the hold function, and deliver the signal (sometimes also in inverted version) for further decoding.

Actions for decoding phase 2 and 3 of the instruction:

The lower contacts of these relays are for decoding that has to take place immediately (to decide what data to put in ALU A and B registers)

Relays R2, R1, R0 select 1 of the 8 registers at output port 1 (via resistors at left and right above the ADD-6 circuit).

Relays A1 A0 select 1 of 3 registers at output port 2 (via lowest contacts in the register bank, with pull-up signals "to_addr"). ( The architecture doc specifies 4 address registers, but the implementation has only 3.)

Relays "A0 slave" and "subtract" select 1 of 2 register pairs (register X or Y) for register mode on port 2 (it uses pull-down signals). The register pair is 32 bits, the shifter selects 16 bits out of these 32 bits (in 4 bit increments). The subtract relay chooses between normal or inverted output at port 2.

"A0 slave" means that this register has the same function/state as relay A0, and it is controlled by a contact of A0 so it switches a little later than A0 itself. This is no problem here because the shifter does not introduce a delay, so the register data will be in time to be loaded into the ALU_B register.

But when A1 and A0 select an address we can not use a slave register, because there is an extra relay level for address decoding (for capacitor-RAM or diode-ROM, not needed in the case of solid state memory). After the address has been decoded, the data will be immediately available to be loaded in the ALU_B register.

A capacitor RAM will be similar to Rory Mangles TIM8 design. Refresh will be different, the idea is that after the cap has activated the relay, it will immediately be refreshed through the hold function of the relay. The circuit of the caps will be such that there is no need to switch between discharge and charge.

Generation of control signals for the shifter and immediate addressing is not yet on the drawing, but this is not very difficult because the timing allows to use an extra level of relays here. Also the Store function is not on the drawing.

Relay Y0 selects if the A0/A1 selection is a pull-up (to 24V, address selection for memory mode) or a pull-down (to 0V, for register mode). Relay Y1 simply disconnects the address selection for Z-page mode, so for Z-page mode only the displacement is connected to the address (bits A0/A1 are not used, in contrary to architecture doc).

Actions for decoding phase 4 and 1 of the instruction:

Decoding for phase 2 is less difficult, because there is time for 2 extra relay levels. At the left side you see the ALU-function signals F3, F2, F1, CY-enable, decimal, Carry-in. When all these relays are inactive, the LOAD function is selected as default. For a ADD function, the relays are set for logic XOR (F1 and F2 active) and CY-enable. For decimal ADD, the same is selected, and in this case also "decimal" is activated, to enable decimal correction in the ALU. ( For decimal ADD, in phase 1 the ADD-6 function is activated).

For logic functions, F1, F2 and F3 are set to correct position.

At the middle low side, there is a decoder that generates control signals to store the ALU result in one of the 8 registers. This is the same register as the register that was output on port 1 of the register bank. Conditional instructions simply disable this signal when the condition is not true.

Incrementing the PC is not yet in the schematic. The incremented PC is always written back to the PC, except when the ALU delivers the new PC contents (in case of a branch or jump).