• XADC Scope

    Antti Lukats04/28/2016 at 18:48 0 comments

    FPGA Design for Zynq that do not use the ARM CPU and not use any I/O either.

    Nonsense? No, actually quite useful, they include XADC block that is connected to logic analyzer so can see the internal ADC reading, scope buffer 32K deep.

    Bitfiles for Zynq ready.

  • 7 ZYNQ's

    Antti Lukats04/19/2016 at 19:10 0 comments

    not really so useful, but included is now script that creates ready to use dummy test bitstreams for existing ZYNQ devices, to allow immediate testing of XVC JTAG server software.

    So take the XVC code from Xilinx github, use the ready made bitstream from LabX and you can check that the software and demon actually works. Sure the jtag server would send JTAG scan data to nirvana, but it would actually talk to the real IP core, so if it works with dummy, it would work with real hardware JTAG as soon as you as make the JTAG port extenal and assign the pins according your board.

  • POF optical cable testing...

    Antti Lukats04/17/2016 at 17:57 0 comments

    Maybe not so impressive pic, but it is done with custom-board LabX design, 12MHz was sent to POF Transceiver, the red light did go into that funny plastic optical fiber and then back into FPGA. Oversampled with 250MHz 4 times, so there are 4 sampels for bit period. I had 250MB/s POF transceiver that I wanted to test.

    The LabX design was made with mouse only no manual coding involved at all.

  • First generic design

    Antti Lukats04/16/2016 at 19:26 0 comments

    so, Artix CSG324 package is supported, so we have

    5 Artix devices supported, there are total 26 devices in Artix family currently, so 21 to go

  • Old dream coming live

    Antti Lukats04/16/2016 at 11:35 0 comments

    I have been working on this over the years, but now it looks like it is close to be nice useable product - starting from 2015.4 release Xilinx as last FPGA company included their JTAG based debug IP Cores for free in free versions of the tools, this opens new horizons and allows the LabX to be implemented in pretty much known FPGA's. Ok for starters Xilinx...

    Milestone 1:

    LabX basic support for all 7 and 8 Series FPGA's: Artix, Kintex, Virtex, Ultrasale, Ultrasale+, Zynq, Zynq Ultrascale+ MPSoC.

    Milestone 2:

    Labx basic board level support for all Xilinx FPGA boards I have access to in our lab.

    Milestone 3:

    Labx basic board level support for all Xilinx FPGA boards that have full public information.


    Scripts and IPI Design are being setup for Artix and Kintex families.

    For TE0725 (Artix A15T, A35T, A100T) board level basic design is ready and openly available.