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Sense Amp Rev B PCB Design Complete

A project log for Ferrite Core Memory Module

A sub-project of the ED-64 Computer to document the development of a 64-byte ferrite core memory module

Andrew StarrAndrew Starr 04/30/2017 at 08:086 Comments

I wasn't able to find a ganged trimpot, unfortunately, so I'll need to adjust the positive- and negative-pulse amplifiers separately.

Discussions

Andrew Starr wrote 04/30/2017 at 23:31 point

Thanks. Start with gains wound down to minimum, then with code on the arduino continually 'flipping' the cores on an address (doesn't matter which), go through each of the 8 bits, adjusting the relevant polarity up until the flip-flops 'SET' inputs are triggered. Then do the same with an adjacent address, adjusting the opposite polarities. Then run a complete memory test, adjust any bits that are still too low for memory locations that fail. Repeat until success :) I imagine it'll be a bit messier than this, but this is the basic jist of it.

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Yann Guidon / YGDES wrote 05/01/2017 at 00:30 point

but I don't see a trimpot in your schematic at https://hackaday.io/project/11179/log/58252

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Andrew Starr wrote 05/01/2017 at 01:00 point

That screenshot is an LTSpice simulation schematic, not the kiCAD one

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Yann Guidon / YGDES wrote 05/01/2017 at 01:08 point

yes, but i have no clue where the trimpot has been put on the schematic....

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Andrew Starr wrote 05/01/2017 at 03:39 point

'Gain is adjustable via R18/R9'

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Yann Guidon / YGDES wrote 04/30/2017 at 08:55 point

This looks nice !

What's your procedure for the tuning ?

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