The idea is to have a FM receiver chip with I2S interface to get the audio data into the digital domain as quickly as possible. The FPGA implements a ring buffer inside the SDRAM memory with an I2S to line out back end. A small controller, probably Arduino is going to to control the radio station and a small display with a all necessary information as FM frequency, rewind metric and memory telemetry. Finally the main controller, a BIG red button to rewind your radio and give superior listen experience. As visible in the picture, the button is the only part I have sourced so far. :)
I do have a Numato Elbert V2 FPGA board. This is probably going to be the base system, it has 4 PMOD connectors to connect to a daughter card (so nice that nobody gave weird names to this kind of boards). This gives me 32 IOs and hopefully enough GND pins for a solidconnection. I will run a 8-bit SDRAM interface through those connectors but signal integrity might be a challenge. Nothing a solid termination cannot fix. The 2 I2S interfaces have to go through a secondary connector wired to the daughter card. This is OK as they are much slower.
I found some candidates for ICs already, see bill of material for details.