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Discussion: FPGA feasible?

A project log for 2018 Open Hardware Summit badge

electronic conference badge for 2018 Open Hardware Summit attendees

oshparkoshpark 04/05/2018 at 03:576 Comments

I received these interesting thoughts from a hackerspace acquaintance which make me wonder if it would be feasible for the $25/badge budget to use an FPGA that would run an open source "soft-core".


This person thought that the RISC-V badge is a great starting point (see earlier project log).  The connector between the badge and the processor could be useful for reuse and upgrades.  However, the connector that was chose is not the most common or easiest to work with.

The Parallax Propeller is an open source microcontroller that is available in a DIP form factor.  It would be nice to provide people with options and the DIP form factor is very convenient.  There are several existing boards that fit that DIP form factor:

It might useful to create some RISC-V modules in the same form factor.  Potentially, one version could have the FE310, and one with a soft RISC-V running in an FPGA.  

Propeller pinout for the MCU interface could significantly reduce the risk of this development.  The badge hardware could be tested with existing hardware while new MCU modules are designed.  The badge could be given away with the least expensive MCU module, and they can upgrade it by building or purchasing another module

An alternative module form factor could be the Arduino Nano pinout for the MCU interface.  That would enable a bunch of MCU choices, and this FPGA board that may be able to implement a RISC-V processor.  The Adafruit Feather form factor is another possibility.

Thanks for your consideration,

Drew

Discussions

greg wrote 04/06/2018 at 04:32 point

The iCE40UP5K is availble for under $6 in these volumes (https://octopart.com/search?q=ice40up5k-sg48&start=0)

This part has 1Mb (128KB) of memory, and there are RISC-V implementations that will run on it (https://github.com/grahamedgecombe/icicle

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oshpark wrote 04/06/2018 at 04:37 point

Thanks for the links. That looks very interesting!  -drew

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oshpark wrote 04/05/2018 at 03:59 point

@Michael Welling any thoughts about using an FPGA?

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Michael Welling wrote 04/05/2018 at 04:35 point

Using an FPGA is certainly feasible but the cost might be an issue. At the qtys you are looking at with the required gate count, it would be around half of your BOM cost.

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oshpark wrote 04/05/2018 at 04:38 point

Thanks for the insights.

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oshpark wrote 04/05/2018 at 03:59 point

@Antti Lukats
any thoughts about if it would be feasible to have an open source soft-core in a FPGA design within a $25 budget for a conference badge?

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