Improved FPGATED core is released now!
After a deep inspection and debugging I have managed to identify a bug in the DMA fetch pointer latch mechanism which has caused some FLI/HFLI pictures not shown correctly. The problem is fixed in the new (v1.1) ted.v core and added FPGATED v1.2 download. In addition the c16.v core has better PLA implementation for ROM chip selects which now resembles the motherboard schematics. This might further improve compatibility with software/demos.
If you are interested in a Plus4 implementation using Papilio Pro FPGA then read the previous project log and check out the sources at Github!
Now its time to work on the drop-in replacement board to test the core in a real C16 or Plus4!