A huge improvement has been made to the TED core Verilog code — one step closer to a 100% accurate TED implementation. Fellow coder DJnICE contacted me and helped identify several bugs in the TED core by comparing emulator source code with the FPGATED implementation, assisted by AI analysis. You can download the updated Verilog core from the Files section. These changes fix multiple demo glitches, especially in the Rocket Science demo, which now runs perfectly.

The new core is fully integrated into my drop‑in FPGATED firmware and released as FPGATED v3.10.

Thank you, DJnICE, for the invaluable help!