Bug fix in v1.0.1 version

A project log for FPGATED

Reimplement the TED chip of Commodore 264 series in FPGA

István HegedűsIstván Hegedűs 08/08/2016 at 21:570 Comments

Original release has contained an incorrect c16_datalatch size in c16.v module. Xilinx ISE has corrected it automatically during synthesis however now it is fixed in v1.0.1

Also reset function is improved. Now reset signal of CPU becomes active while user keeps reset button pressed.