I have been quiet recently however in the background I have not stopped development of FPGATED.
Current focus is on creating a Plus4 version for Papilio Pro FPGA board. These are the statuses of my progress
1. SDRAM controller for FPGATED using Papilio Pro's onboard sdram. Ready.
2. Bootstrap to load ROM files from flash chip to sdram on startup. In progress.
3. Implement Hannes/Csory ram expansion, plus develop new RAM extension method. Planned.
The SDRAM controller works perfectly and makes use of the whole 8MB RAM of the Papilio Pro board. 4MB will be available as RAM for TED and 4MB for alternative ROM images (Original Kernal/Basic, Jiffy DOS, Function ROMS, Cartridge ROMS).
I will release next code when point no 2 is done. Hopefully soon so come back to see.