During the last years I was away for a while from hackaday, however I am resurrecting my project now. 

Despite my silence I was not completely passive and I have developed an FPGA Plus4 based on FPGATED core and moved the project to Papilo Pro platform. See https://github.com/ishe/plus4

The Plus4 core uses the sdram of Papilio Pro board, has flash storage for extra Kernal, Basic and Cartridge ROMs. I have developed a special kernal to do the switching between ROM versions and ROMs are saved together with the FPGA bitstream on the onboard SPI flash. Here are some of the implemented features:

- sdram controller for the Micron MT48LC4M16 64mbit sdram chip, synced to Plus4 bus cycles

- a special bootstrap code to load ROM images and FPGA Plus4 configuration bytes during startup from SPI flash to sdram

- a special Plus4 Kernal developed in assembly to handle Kernal switching (Kernal starts when ESC key is pressed during power up or reset)

- half of sdram is used for ROM images. 16x Kernal, 16x Basic, 16x Function low/high, 16x Cartridge1, 16x Cartridge2 ROM locatrions (4MB for ROM images)

- prepared addressing mechanism to use the other half of sdram for RAM extension (extra RAM is not yet used)

...and finally I have identified a bug in FPGATED core that caused some of the FLI demos not to work correctly (especially the ones created by MMS. E.g. Boredom). The bug has just been fixed and I am now testing this latest build. Now all FLI images are displayed correctly so the core is highly compatible with the original chip. Bug fixed core will be released soon in the coming weeks.

from now on I will concentrate on creating a small snap in board for replacing dead TED chips.  The challenge here is the analogous Color PIN of the chip which provides a PAL or NTSC encoded signal. Probably an external chip will be needed that encodes the digital signal, however if someone has some usable idea for it, don't hesitate to contact me!