Design

The diode clock uses four radio-frequency power supplies. To reduce emissions, they are driven with a spread-spectrum signal produced by the DDL04. The spectrum of this signal is tuned to give good performance with DDL V2.x logic boards. Here's a simplified schematic (5V power supply components omitted):

Since it's an eye chart on this page, here's a pdf version.

The goal is to provide a spread-spectrum clock with a selectable spreading width around an input clock source. To do this, a variable divider clocks a 15-stage linear-feedback shift register (LFSR) producing a pseudo-random bit stream. This bit stream then modulates the original clock signal to spread the spectrum, which is output through coax to the four DDL02 power supply boards. Two opposing clock phases are produced by the board, so that adjacent DDL stacks can be clocked 180-degrees out of phase, (theoretically) reducing RF emissions.

The system is clocked by a standard oscillator "can", nominally 6 MHz, although something around 9 or 10 MHz might be a better choice for DDL V2.x - more on that later. A 74AC74 flip-flop divides the crystal frequency by two. A 74HC4017 decade counter combined with dip switches and a diode-OR gate allow a programmable divisor between 1 and 10, effectively setting the clock spreading width. A 15-stage LFSR constructed from a pair of 74HC164s produces a pseudo-noise bit stream based on the output of the '4017. Although the shift-register is long enough for a 16-bit LFSR, an extra XOR gate package would be required on this board to implement the feedback. The 15-stage LFSR outputs a stream of (2^15 - 1) = 32767 pseudo-random bits before repeating.

The output of the LFSR is used to selectively invert the original clock signal in another XOR gate, effectively modulating it by the LFSR's spectrum. The net result is a spreading width that is an integral divisor of the original clock frequency. The remaining 74AC74 flip-flop is used to synchronize the modulated clock, preventing runt pulses which wouldn't make it through the DDL02 power supplies.

The output driver is a 74AC244, with each 50-ohm jack driven by two gates. 74AC logic has symmetrical output impedance of around 12 ohms. An 86.6 ohm resistor in series with each output raises this to approximately 100 ohms, and two such outputs paralleled provide a good match to 50-ohm cable and enough current to drive it.

LFSR Watchdog

The combination of D5/C7/R6 deserves a quick mention. It functions as a crude "LFSR watchdog", re-starting the LFSR should it ever become "stuck." The LFSR has only one forbidden state: a register full of zeros will remain full of zeros. Unfortunately, that's exactly the state that the /CLR line puts the 74HC164 into, and being a serial-in, parallel-out register, there's no way to jam some initial state in "from the side." Using a power-on reset would require clocking in some non-zero initial state. The LFSR watchdog implemented here takes a different approach, sampling the bits as they move through the register. As long as there are some ones shifting though, D5 keeps C7 charged, and the associated Schmitt-trigger inverter output low. Should a long-enough string of zeros occur, C7 will discharge through R6, the inverter will flip and start inverting the feedback to the register, pumping in ones to restore a valid state. As soon as the ones start circulating again, C7 gets charged back up, and the feedback polarity is restored. Since the LFSR can output at most 14 consecutive zeros in normal operation, the RC time constant is easily chosen to avoid false-triggering, but quickly detect a stuck state.

Substituting Parts

Because of the low speeds involved here, I used 74HC and 74AC parts interchangeably. The notable exception is the 74AC244, which is used to drive four 50-ohm coax lines. An HC can't handle the currents involved, so don't substitute. All the parts except the 74HC4017 are also made in a 74AC version, so if another dividing mechanism is used (like a 4-bit loadable counter), this circuit could be used with much higher clock speeds.

Noise Period

The LFSR uses a maximum-length feedback polynomial:

which has a period of 32767 clock cycles. The bandwidth of the central spectral lobe and the pseudo-noise repeat period are determined by the spreading divisor setting. One of the design goals was to have the noise repeat period in (or close to) the infrasonic range to reduce the probability of detectable interference if any EMI did leak from the clock. This table shows some of the settings (others omitted for brevity) for a 6 MHz crystal oscillator.

Design Files

The Eagle design files are shared here, and boards can be ordered at OSH Park.

I haven't put together a formal BOM yet - I'm going to make one for this as well as the three flavors of the DDL01 shortly. For now, the parts are pretty clear on the silkscreen, except perhaps "RSSD" (aka R6) and "CSSD" (aka C7) in the LFSR watchdog detector - 10k and 1n work well here.

Here's an instance of the board I populated this week to collect some data:

For testing, the crystal oscillator can is not mounted, and a coax pigtail is wired in its place (with a series resistor and a pair of diodes jammed in there for protection from ESD and over-zealous signal generators). I only soldered on one SMA jack - no sense mounting $20 of hardware just to grab some data. When I built this particular board, I forgot to populate the LFSR watchdog capacitor, CSSD (aka C7) - don't try this at home, because you'll shorten the LFSR period significantly, then waste a day or so trying to figure it out.

Next: analyzing the output in the time and frequency domains