Currently trying to jump to the last car of efabless train :)

- made a few test designs for TinyTapout that goes with efabless 130nm process;

- and also submitted 2 open source test designs to efabless 1st 180nm process that should go through GlobalFoundries

Nothing fancy, because everything is done through Verilog  - you can actually draw your schematics in Wokwi but it's eventually converted to Verilog as well. Good thing is that self-made latches are translated to low level almost as is:

This is a Muller gate (or C-gate) and if it will work as intended on actual chip then it means async designs are very possible with this Yosys driven process :)