Trying other ways to make chips

A project log for Shared Silicon

Silicon proven way to reduce the cost of integrated circuit manufacturing by collaboration

SHAOSSHAOS 12/05/2022 at 03:272 Comments

Currently trying to jump to the last car of efabless train :)

- made a few test designs for TinyTapout that goes with efabless 130nm process;

- and also submitted 2 open source test designs to efabless 1st 180nm process that should go through GlobalFoundries

Nothing fancy, because everything is done through Verilog  - you can actually draw your schematics in Wokwi but it's eventually converted to Verilog as well. Good thing is that self-made latches are translated to low level almost as is:

This is a Muller gate (or C-gate) and if it will work as intended on actual chip then it means async designs are very possible with this Yosys driven process :)


matt venn wrote 12/05/2022 at 10:38 point


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SHAOS wrote 12/06/2022 at 03:24 point

Hi, Matt!
Thank you for TinyTapout :)
Looking forward to participate in TT03 ;)

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