I've added a testbench that verifies that a switch block can route a signal into and out of a logic block. I was originally writing a testbench that programmed a full adder in the logic cells, but manually configuring memory is tedious and mistake-ridden. I backpedaled and decided to just use one XOR gate, and XOR two signals and send it out the top of the FPGA, but that is still a lot to do. I've included the broken testbench in the repo just in case.
I decided I would release the code under the GPLv3. I'll attach the repository to this page shortly.
The next step is to parameterize the design, which will make it easier to use a more powerful logic cell.