FPGA SoC fully written in SpinalHDL

A project log for SpinalHDL

SpinalHDL is an alternative hardware description language designed to provide many features that are missing in VHDL and in Verilog.

Dolu1990 • 09/04/2016 at 18:11•0 Comments

Pinsec is the name of an little SoC fully written in SpinalHDL.

This SoC has currently following features working on FPGA :

AXI4 interconnect for high speed busses
APB3 interconnect for peripherals
RISCV CPU with instruction cache, MUL/DIV extension and interrupt controller
JTAG bridge to load binaries and debug the CPU
SDRAM SDR controller
On chip ram
One UART controller
One VGA controller
Some timer module
Some GPIO

Some documentation is available here : http://spinalhdl.github.io/SpinalDoc/spinal/lib/pinsec/introduction/

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