CMOS Game of Life

Description

The goal of this project is to create a hardware implementation of Conway’s Game of Life on an 8x8 LED grid. This chip is designed in a 0.6 µm CMOS process to be fabricated on a 1.5 x 1.5 mm 40-pin MOSIS “TinyChip”. The CGoL implementation has one standard start configuration, R-pentomino, as to limit the size of the hardware needed. The chip consists of both custom and synthesized components. A custom register file was designed as to suit the needs of the project. The remaining components were synthesized from Verilog. The chip has been verified in simulation. Currently, Evan and I are waiting for the chip to be fabricated.

Here is a video of it working!

and all the verilog code is here:

https://github.com/vaibhavviswanathan/CGoL/blob/master/everything.sv

Discussions

Yann Guidon / YGDES wrote 12/16/2017 at 14:38

Do you have a high-resolution picture of the layout ? :)

Edit: ooops, there it is :

Are you sure? yes | no

matseng wrote 06/29/2017 at 04:19

I wish there was a distance course at some uni where anyone could sign up to and learn about chip design and also get free access to Cadence and a subsidized fab.....

Are you sure? yes | no