TI-99/4A memory extension with Pipistrello FPGA

64 megabytes RAM expansion for the TI-99/4A using the Pipistrello FPGA board and a buffer board.

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What would be the weirdest way to implement RAM extension for the TI-99/4A vintage computer? Not quite sure, but doing it with a Pipistrello FPGA could qualify. The pipistrello FPGA board features the Xilinx XC6SLX45 FPGA, which is one of the largest capacity FPGA chips available to hobbyists.
The TI-99/4A was my second computer after the ZX81 as a kid. I recently reacquired one. It was and is in a pretty beaten up shape, but I did get it to work. it came with some cartridges, but nothing else. As a kid I had the extended basic cartridge for the TI, but I realised that I could not program it in assembly without a memory expansion. That was prohibitively expensive for me, so I went on to ZX Spectrum to learn assembly programming.
Fast forward 30+ years - now that I have a TI in working order it was time to get memory extension done. I thought it would be fun to implement that in an FPGA chip, as that would then be a great basis for all kinds of additional TI extension goodness.

Update 2016-09-26: SD card access now works

This is one of the first runs of my memory dumper "cartridge" reading data off SD card. The code reads the master boot record, then parses the partition table etc and finally reads and shows the contents of the root directory. This code only understands FAT16 partitions, and does not support yet SDHC cards, so it is running of a 2GB regular micro SD card.

This is just the starting point, the bigger step is to write the driver code so that the SD card would appear as normal TI disks.

Update 2016-09-24: GROMs moved to RAM

So far in this FPGA design I've kept the GROM memory contents stored on the FPGA's block RAMs, emulating ROMs. The ROM contents became initialised as the FPGA was initialised. But that did limit the amount of GROM the design could include and also made it slow to modify GROM contents. So now I set aside a one megabyte region for GROM contents, and using the PC USB loader I can initialise the GROM contents in the external memory.

Below I have XB2.7 suite running on the TI console. This is usually done using a cartridge, housing 512K of ROM and 120K of GROM. Now both are being served by the FPGA - along with the memory extension.

I also tested RXB2015 (another extended Basic), and that worked too. RXB supports SAMS memory, so it was great to see that being detected and working nicely.

Update 2016-09-20: SPI interface and memory dumper

Now there is an SPI interface in place. I adopted it from an earlier design of mine. Testing the SPI requires some driver software, so I put together a simple program to dump memory as a starting point for the SPI testing code (the SPI drives the SD card interface). The memory dumper app includes code to display text on screen and keyboard processing, so the basic building blocks are there. The memory dumper program proved immediately useful, as I finally got the SDRAM interface robustly working. Since PC connectivity is already there, I utilised that for hardware debugging: pressing the period key in the memory dumper copies the values of some hardware registers to memory extension, allowing the PC memory reading capability to reach those values without having to modify the FPGA. The memory dumper itself is written in TMS9900 assembly language and runs in the cartridge memory space (address range 6000..7FFF).

Update 2016-09-04: PC connectivity

In a hobby project like this one, I usually want to build things in an incremental fashion, one small step at a time. So far the project has advanced pretty nicely by just going after the low hanging fruit - basically implementing more or less existing functionality in the FPGA (existing as in RAM extension, cartridge emulation etc.).

Sometimes the small steps just are not possible. For me it came with connectivity. I wanted to finally get to a phase where the modern world would meet the TI to the extent that I could push easily software into it. So I wanted to have PC connectivity - but not your average with a serial port. This project is running on a very high-performance FPGA, something better surely can be done?

Well I got something much better done. I still have the UART for serial communication, implemented in the FPGA. But it is not the CPU of the TI-99/4A that is communicating with the UART. Instead, there is a hardwired state machine that provides PC access to the memory space concurrently to the TI, basically while the TI is running full speed there is sideband channel that allows a PC to issue commands using the serial port to read and write to memory, without the TI noticing. Serial communication is currently running at 230400 bps, but that could be pushed higher. In practice the serial traffic happens over USB thanks to the FTDI chip on the board.

Alas, that turned out to be more work than I perhaps expected. There were a whole bunch of things to work on, all which were pretty much necessary to complete this feature:

  • Define a protocol that is simple enough for a simple state machine to understand, yet...
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  • SD access now works

    Erik Piehl09/26/2016 at 18:00 0 comments

    I added SD card support VHDL code, but did not have the time until now to debug it. Now I have a TMS9900 assembler program which successfully displays the root directory of a FAT16 partition.

  • Super AMS compatibility done

    Erik Piehl09/21/2016 at 20:14 0 comments

    I modified the memory paging side of the design somewhat, so that the paging is controlled using the same bits as with "Super AMS" memory paging unit. This required the addition of the support of the TMS9900 "CRU" memory space - but in a limited manner. Now the the FPGA based memory expansion passes the SAMS memory tester. This is very nice indeed - also since I don't have to write memory test code myself :)

  • SPI interface and software development

    Erik Piehl09/20/2016 at 17:54 0 comments

    Real life kept me busy, but I finally had a moment and added SPI interface to the FGPA design. It allows the use of SD card, but needs driver software, so I also have spent a little time building some software. At this point the software is a simple memory dumper, controlled by button presses. Very useful for hardware testing, and now that there is simple user interface capability it will be hopefully easy to get the SD card driver side done and tested.

  • PC connectivity using DMA style approach

    Erik Piehl09/04/2016 at 20:21 0 comments

    Now I finally have an easy to way to push software to the TI. I built support for serial communication (over USB) at 230kbps allowing me read and write the memory expansion concurrently to the TI - without the TI noticing. This is hugely useful also for software development and debugging.

  • GROM functionality now done by the FPGA

    Erik Piehl08/26/2016 at 20:12 0 comments

    After some debugging sessions, I got the GROM address counter bugs fixed and now the FPGA alone also integrates the extended basic cartridge.

  • ​ROM and ROM page switching moved over to FPGA.

    Erik Piehl08/24/2016 at 06:35 0 comments

    I wish there was more time to work on this, but at least I could take a simple step of moving the extended Basic ROM in the cartridge port into the FPGA, along with the ROM page selection logic. Thus now the only thing requiring the cartridge port to be occupied at all is the GROM section, which needs to move over to the FPGA next.

    Obviously having cartridge functionality in the expansion bus is probably not exactly proper behavior, but I don't have the extended basic cartridge. I suppose the FPGA could have a sense mode, to see if there is a cartridge driving the databus, and if not, then take over and become the cartridge.

  • SDRAM controller working...

    Erik Piehl08/19/2016 at 08:05 0 comments

    Yesterday got the SDRAM controller working. More testing and validation required, but it is nice to have 64 megs of memory! Memory paging unit is still not working completely.

  • SDRAM controller implementation started

    Erik Piehl08/16/2016 at 06:59 0 comments

    One of the next steps in this project is to integrate all the functions on the other boards into the FPGA. I also want to start using the external LPDDR RAM memory. The use of that is not trivial, but this FPGA includes a memory controller. The problem with it is that this component is highly configurable and complex. But I did manage last evening to go through the first step, which is to instantiate the controller and have it drive the clocks in the logic. That means that the PLL in the memory controller is now generating a 100MHz clock that drives the logic. Next need to build a state machine to control memory writes and reads, and hope for the best...

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Bill R Sullivan wrote 08/31/2017 at 03:57 point
I'm very interested in this project, as I need a minimum of 256K for my X4th99 project, and maybe only 128K for my TI BASIC+ project for my TI-99/4A with F18A video and USB adapter w/wireless keyboard that use NanoPEB or CF7A+ expansion systems.  The X4th99 project is well along using a 1 MB SAMS card in a conventional PEB.  I have previous experience developing Forth+ for a 2 MB 9640 Geneve which was released in  late 1993.

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