One of the next steps in this project is to integrate all the functions on the other boards into the FPGA. I also want to start using the external LPDDR RAM memory. The use of that is not trivial, but this FPGA includes a memory controller. The problem with it is that this component is highly configurable and complex. But I did manage last evening to go through the first step, which is to instantiate the controller and have it drive the clocks in the logic. That means that the PLL in the memory controller is now generating a 100MHz clock that drives the logic. Next need to build a state machine to control memory writes and reads, and hope for the best...