Reuse an old broken laptop panel with a Raspberry Pi with a FPGA board.
This project simply use Verilog samples from Xilinx XAPP460 for DVI in, and LVDS serializer implementation together.
The panel is a LP089WS1-TLA2 1024x600 18-bits.
The FPGA board minispartan6+, I used this board because of the HDMI in port, but since there is no need of external RAM and the used Verilog is intended at Spartan3, I think a smaller Spartan3 board with HDMI in should work.
Since there is only video signal, panel must be configured in Rasperry Pi config.txt, eg for LP089WS1 :
# force console size
hdmi_cvt=1024 600 60 3 0 0 0
# panel is 18-bits so dither from 24-bits
LVDS input is operational, the last step is to process hdmi output
The good news is that DVI and LCD signal protocol are very
similar : pixel, hsync, vsync and clock. The main difference is the
electrical signal, LCD uses LVDS and DVI uses TMDS, they are both
differencial but incompatible.
Xilinx Spartan chips are able to natively manage these two
types of electrical signal which will highly simplify the requirement.
Xilinx exposes a DVI in/out verilog implementation in an application note, thats great since I just needed to create an interface between the
LVDS controller previously used and the DVI input example.
To test, I switched to minispartan6 which has an HDMI input
connector. The design does not change very much, both spartan 3 and 6
manage LVDS and TMDS, I only modified the pins connections for LVDS.
Both verilog controllers manage the
serialization/deserialization of the two signals and expose the
resulting red/green/blue/vsync/hsync signals.
It is actually that simple, connect rgb, sync and clock between the two controllers !
There is just a small problem, DVI output 24bits color and the panel takes 18bits but a truncation seems sufficient.
Now that electrical connection works, it is time to get data signal.
Lvds has 4 differencial signals on 8 pins :
The protocol is not so complicated : just send one
pixel after another, and some sync signal (Vsync and Hsync). Since the panel has
a fixed size (1024x600), the clock must match the desired screen
refresh rate :
Clock = ((width+hsync) x (height+vsync))/refresh
For my panel :
(1024+280)*(600+25)*60 = 48.9Mhz
I initially used Spartan 3e based board (Papillio One).Xillinx Spartan supports LVDS signaling but there is a constraint in assigning pairs which must be next to each other, the UCF file looks like :
NET "channel1_p" LOC = P40; # A5 NET "channel1_n" LOC = P41; # B10 NET "channel2_p" LOC = P60; # A8 NET "channel2_n" LOC = P61; # B7 NET "channel3_p" LOC = P62; # A9 NET "channel3_n" LOC = P63; # B6 NET "clock_p" LOC = P70; # A12 NET "clock_n" LOC = P71; # B3
Thanks to github, I quickly found an already done Verilog implementation with a parallax sample.
I just needed to adapt to the panel :
First step was to find proper pinout from the small 40 pin
cable of the LP089WS1. I initially wanted to reuse the original cable, cut and solder it
to a prototype board. Unfortunaly these connectors are very fragile and
soldering one side actually desolder the other ...
So I choose to buy an already made cable from ebay. It
appears that each LCD panel has his own pinout schema : you can't use
any cable, you must choose one for your panel. LVDS is only a 4
differencial signal (8 pin), other signal are some GND and Vcc for LEDs
and panel - randomly assigned accross the 40 pins by manufacturer. Ebay
sellers provide cable with only 12 to 16 output to interface with.
Once received, I imagined that the seller will give me the
pinout schematics, unfortunaly he do not know more than me about that. I
needed to check every pin with the panel datasheet to figure it
Before going further with data signal and FPGA stuff, I tested the LED with 5V as stated by the datasheet (at this point I was'nt sure the panel was still working).
Actually I needed to supply the panel (3V3) the LED enable pin and LEDs supply itself. And it worked ! A nice shiny dark gray.