01/19/2021 at 03:21 •
The previous log found a weird and unexpected behaviour, a sort of parasitic diode, in a high-speed low-voltage low-power germanium transistor.
So let's see if this hypothesis holds for other types of transistors and I can test other high speed parts I collected in the last years.
Let's start with the classic MPSH81 : 600MHz, PNP, 50mA, 20V, hFE>60 (@10V 50mA=>Ib=1mA), Nothing to see here but it's a sort of baseline and you get the idea.
hFE Vbe (mV) Ic (mA) 1 119 731 1.1 2 127 735 1.2 3 128 727 1.2 4 121 728 1.1 5 129 727 1.2
Current is recommended in the 1 to 30mA range, and frequencies up to 250MHz.
Collector-Emitter Breakdown Voltage is 20V, which is probably out of range of the tester.
I only have about a hundred pieces but it's enough for simple tests.
Then we have the BF970: Silicon PNP, Ft: 900M to 1GHz, 35V, 30mA, hFE>25. At this voltage, no breakdown should be visible:
hFE Vbe (mV) Ic (mA) 1 42 707 0.39 2 42 697 0.39 3 41 698 0.38 4 41 697 0.38 5 44 697 0.41
That sample looks well binned :-)
So far, nothing unusual, the leakage is not detected and the operating voltage is high enough. So let's turn to Germanium with parts in the A series.
AF439 is a Germanium PNP rated at 15V, 10mA, GBWP=400MHz (or 800 depending on the sources) and hFE>10. Bingo !
hFE Vbe (mV) Ic (mA) Drop (V) Ice0 1 10 442 6 1.96 2 10 435 6 1.93 3 10 438 6 1.57 4 9 434 5.9 1.69 5 9 434 5.9 1.76 6 9 437 5.9 1.64 7 8 431 5.9 1.65 1µ 8 11 431 6 1.94 1µ 9 10 433 6 1.80 1µ 10 11 433 6 1.67
Same behaviour with a pair of AF280 ! (15V, 10mA, 60mW, 550MHz)
hFE Vbe (mV) Ic (mA) Drop (V) Ice0 (mA) 1 11 342 6 1.52 0.12 2 12 465 6 1.38 0.001
As the Vbe decreases, the Ice0 increases...
I don't want to bend more TO-50 pins for a reference where I have so few parts, but I think I made my point.
Back to some old good AF138:
PNP germanium diffusion alloy ... 12V, 10mA, hFE>60
hFE Vbe (mV) Ic (mA) Drop (V) Ice0 (mA) Ices 1 404 258 4.3 2.03 0.27 2 198 249 2.3 1.99 0.36 3 222 244 2.9 2.20 0.7 1µ 4 44 270 6.6 2.13 0.002 5 322 254 4.1 2.44 0.86 6 66 314 6.6 2.6 0.11 7 277 257 3.3 2.48 0.5 8 265 243 3.6 2.1 0.92 1µ 9 321 264 3.8 2.19 0,63 10 312 259 3.8 2.17 0.66
As noted before, higher leakage could be mistaken for higher gain.
I wonder what Ices is... Oh and number 4 is out of spec ;-)
Despite its leakage and the inability to work as pass transistor, I kind of like this reference, of which I have 1.6K which allows me to build some interesting digital devices, probably slow and medium I/O ports and interfaces, probably using DCTL.
And now, the AF306:
GBW: 100 to 500MHz (?), 15mA, 18V
hFE Vbe (mV) Ic (mA) Drop (V) Ice0 (mA) 1 32 293 0.34 2.12 14µ 2 16 277 0.18 2.46 21µ 3 16 393 6.2 2.83 1µ 4 35 298 0.36 2.56 18µ 5 33 288 0.32 2,03 31µ 6 13 391 6.1 2.91
In their TO-92-like package and with only 50 of them, I don't know what I'd do with them, as they are less consistent than the other references.
And AF178 :
PNP 25V, 0.01A, 80-200MHz, hFE>20
hFE Vbe (mV) Ic (mA) Drop (V) Ice0 (mA) 1 122 307 1.3 2.19 0.72 2 248 308 2.6 2.11 0.11 3 122 302 1.3 2.38 0.11 4 117 299 1.2 2.33 0.041 5 79 278 0.85 2.17 0.058
I don't see how to best use them, though I have a hundred of them... Their current is too low, only the voltage is higher.
The AF200 might be a precursor to the AF240. I can't find its frequency but it's a mesa type.
10mA, 25V, hFE > 30, ft=10MHz ??
hFE Vbe (mV) Ic (mA) Drop (V) Ice0 (mA) 1 16 416 6.2 2.28 2 14 278 0.15 2.38 3 20 293 0.2 2.28 4 12 259 0.13 2.47 5 22 287 0.23 2.52 4µ 6 13 283 0.14 2.34 7 13 269 0.14 2.57 8 20 409 6.2 2.73 9 18 294 0.18 2.36 10 20 288 0.2 2.39
This generation starts to solve some problems of the previous Ge generations, in particular very low leakage without raising Vbe too much. But the gain drops...
My hypothesis that the "parasitic diode" is structural with a type of Ge transistors seems to hold water. It might be due to a very low breakdown voltage, a non-controller Zener effect that could be due to the need for higher speeds and thinner junctions...
The reverse drop depends on the family so it should be related to the fabrication process.
Now, I don't have more Ge trannies but some interesting ultrafast silicon ones, such as the BFG425 which is rated at 4.5V max for 25GHz@20mA. I wonder if the same diode appears again... But does it matter for pure ECL topologies ?
https://northcoastsynthesis.com/news/transistors-for-the-perplexed/ explains this very well : this value is called Veb0 and this is inherent in the construction of all transistors, though it is more apparent in Ge because the bandgap is narrower than silicon : Silicon is in the 5V+ range where Ge is in 1.5-3V range. This is random avalanche effect often used in noise generators, such as explained at https://electronics.stackexchange.com/questions/207192/white-noise-generator-transistor-voltage-question.
Of course, even Wikipedia mentions it.
01/17/2021 at 10:12 •
I have already covered the test of hFE + leakage of Ge transistors there but since I bought the handy device seen below, I use it very often ;-)
The transistor test mode is particularly interesting because it provides data beyond the old hFE. It's good at spotting "lemons" and in the case of the AF240 I had a surprise :
The gain is consistently low, between 8 and 10, and it's rated at 25 though the datasheet might use a different measurement circuit. But it's low. And quite bounded. Ic is rated at 10mA (yes it's a low-power device) so the base requires a 1mA current to get things going...
The Ube varies between 0.32V to 0.46V, more than the other Germanium from other batches and other types (often as low as 0.1V). Increasing this value is probably the cost paid to have no detectable leakage current, but I'll live with that for the project in question.
But the emitter-collector diode is new and unexpected. The forward voltage (between 1.2V and 1.5V) should never happen in a normal circuit but... the diode should not exist anyway, right ?
I see no mention of this parasitic behaviour in the datasheets (here its sibling, the AF239)
Note that Ib must be < 1mA. This is a very fragile part.
As you might remember, the AF240 is a "mesa" type, made with epitaxial deposition. It's designed for the fast ft=500MHz and the supply is reduced to 15V max. I wonder what causes/creates this parasitic diode, that is usually found in MOSFETs.
As discussed in the comments, it appears that the 1.3V diode is in fact 2 diodes in series :
- the normal base-collector diode at approx. 0.3V
- the normal base-emitter diode is approx 0.3V too but apparently in parallel with the unexpected reversed 1V diode
The new hypothesis is that this could be the breakdown voltage of the base-emitter side, which would be lowered due to the tuning for speed. So this would be a side effect of the intrinsic fabrication process of a speed-oriented part, as the photograph of the internals show no diode.
Now I wonder if/how other UHF transistors exhibit such a parasitic diode and what their value is...
Can anyone chime in ?
Anyway, the AF240 seems to be precisely appropriate for ECL operation, with its low gain, low operating voltage, low current, undetectable leakage, and the 10mA rating almost gives it away.
05/25/2020 at 04:58 •
For the newcomers, have a look at the log 2. moving forward of a related project. The comments are great too :-)
So I want to make ECL gates. I want to make them fast and if possible reduce the amplitude and frequency of the PSU's "digital noise". Oh and I would love to have an even lower supply voltage, because about half of the power is burned by the common resistor, that wiggles between 0.8 and 1.2V. If I could win maybe 0.5V there, the PSU would have to supply only 1.5 or 1.6V and save 20 to 25% power. Furthermore I might want to "stack" layers of ECL circuits later...
According to @Julian, reducing the current below 2mA starves the circuit and the speed is reduced, so I'll stick to 2mA for now and try to get the equivalent of the 470 ohms I now have.
What that would bring me :
- The ability to change the settings and working points of the whole circuit with current mirrors spread around the PCB and trim the values with one pot,
- reducing the operating voltage (and power), or increasing the current at will to see the effect on the speed
- reduce power noise and decoupling
There is not much margin though : 0.8V is already low, and a degeneration resistor will already eat 0.1 or 0.2V and the transistor's Vcesat can impose limits. The complexity of the system would be overkill while a simple resistor already works rather well.
But there is something else : the lower the resistor, the lower the swing at the common node, and the lower the sensitivity of the inputs... Maybe a transistor could help there too ?
Looking at https://wiki.analog.com/university/courses/electronics/text/chapter-11, I find this interesting circuit :
but this is a current mirror : this means that to get 2mA in the output (which can be replicated/multiple) there must be another place where 2mA is sunk. Which is not great for power savings. Things start to get complicated from there, if I want to reduce it to 200µA for example...
R2 would be about 50 ohms and drop 0.1V at 2mA. Energy saving means I should get the lowest Vce, so it must be (almost) saturated. Which means : pumping significant current in the base. Which means that the R2 drop would also increase because of that base current and might reduce its effectiveness. The transistor's gain should thus be high to reduce base current and Vce, but all those counter-effects conspire to make the transistor current sink overly complicated.
After all : looking at Motorola's MECL Data Book, no transistor is used in the major old families:
- MECL I : 1.24K
- MECL II : 1.18K
- MECL III : 365
- MECL 10K : 779
The high-side resistors however are lower than my values : 100 (MECL III) to 300 (MECL I & II). I could investigate reducing my values but this comes at the prince of increasing the current...
Do I really need a sink transistor ?
05/24/2020 at 17:15 •
My logs about speeding up the 2N2369A have brought a lot more of insight or CDC's RTL logic, as well as confidence in my methods, and the results are very good. So the next step it to explore the following technology node : ECL.
One defining angle of my exploration was not much the absolute raw speed but about finding the "sweet spot" where a small increase in speed was not at the cost of a large increase in power. I want to apply this angle to ECL as well and see if/how I can reach a similar (or better) speed/perf ratio.
I will use a similar method as the 2N2369 : measure the RingO9 speed so the data can be easily compared. In the beginning however I will use Silicon transistors, for 2 reasons :
- If I use 2N2369As again, the comparison of the topologies is easier.
- Flastad's sim has no germanium transistor in his models
Another question is where to set the power supply voltage. Early sims show that I can get down to 2V easily.
(yes the ref's capacitor takes a while to load)
Then I found that more tweaking can occur :
- reduce the resistors
- if fanout is 1 then drop the common collector output drivers and just drive the next stage directly
- fine-tune the Vref
And I can reduce the supply even more to 1.5V. The tuning parameters become the Vref and the common low-side resistor. Here are 2 examples with 2 values :
When the common resistor is lowered, this increases the current but also the swing so the Vref must be adjusted.
Looking at some 5V schematics I see the pull-ups at about 50-300 Ohms, and the common resistor at about 300-1K. Here I have reversed the ratios but starting from 470 Ohms lets me compare the topologies with the CDC-RTL that uses the same value.
Increasing the common resistor might increase the sensitivity but also reduces the current/slew rate (supposedly) while at the same time reducing the swing (is that good or bad ?).
Another aspect of this approach is that we are confined to only single-layer types of gates : no series-dotting and the associated functions. It's (N)ORs all the way down, like with RTL. But each ECL gate has 2 complementary outputs so each count as 2 RTL inverters !
Series-dotting brings more logic functions to the table though. Latches and XORs are essential 2nd order circuits that are dearly required.
A non-insignificant part of the consumed current comes from the voltage reference. The typical circuits use some sort of regulator... I am now wondering how I can reduce the current while keeping the minimum number of parts. At this moment I think of a transistor on the high side (collector and base tied to make a diode) and a pull-down resistor (value TBD).
So we can start with this rule-of-thumb : each layer of transistor is separated by a diode (Vbe) drop. This keeps the regulator simple yet with low impedance.
A few sims later and I get this inverter design :
Vref is at 1.5V : there is only 0.5V drop in the transistor but only 130µA is drawn. This can be tuned with a potentiometer tied to the ground.
The signal swing is 1.3-1.8V : +/- 0.3V around Vref, nicely symmetrical :-) I had to tune the upper resistors a bit and it's good.
Surprisingly, and I couldn't guess from a test with an individual gate, the current of the 5 gates is only 9-12mA (2mA/gate ? :-) ) so decoupling will not be hard.
With 390 ohms and the emitter going from 0.85V to 1.2V, the base current swings from 0 to 0.5mA so the transistor is barely saturated : no need to fight hard to drain the base charges...
The 470 Ohms common resistor goes from 0.85 to 1.2V, that is 1.8 to 2.5mA, or 2.2mA average. A transistor-based current sink would be appropriate to reduce the current variations and the PSU noise.
03/29/2018 at 01:14 •
@Blair Vidakovichrecently added a great page to the #Hackaday TTLers:The Electronics of IBM Standard Modular System Logic
He reviews the individual ECL gates of SMS modules and they are pretty simple :
Compare this to the "early ECL" diagram I mentioned earlier and see how they match :
Unfortunately, the IBM way has 4 power rails (with 6V differences). That's a LOT, and a significant waste, but at that time, transistors were very expensive...
02/01/2018 at 15:45 •
I came across this excerpt from the AD9712 datasheet :
It's like an "ECL kit" !
I have more books to look at...
09/29/2017 at 11:05 •
ECL is old but still incredibly interesting. My interest is renewed after I found a few ECL databooks/appnotes/guides on eBay. Fairchild, Motorola, NatSemi... Some of those books are older than me (1972 for example) but still fascinating and particularly relevant for this project (and for #YGREC-ECL ) because they contain a lot of insight into the design process and the structures of the integrated circuits. The Motorola MECL book is particularly impressive as it explains the topologies, which would have taken years to invent myself...
For example, I know about "series gating" (serial connection/cascading of differential amplifiers) but this technique has some subtleties that the book explains, so I might implement a better-than-crude version. I found the same diagram on the web, thanks to knowing the right keyword :
The topology of the resistor-diodes networks on the right of the circuit is not something I would have imagined myself. The level adaptation on the left (transistor with base on X) is another non trivial circuit for me...
Right next to this circuit, another is shown that implements "dotting" where diff amps are paralleled, before driving the amplifier. This creates OR-AND networks and saves some latency.
This increases my "vocabulary" and I have more and better options for the design of discrete and fast digital circuits :-)
(note: a brief summary can be found there but nothing beats deadtree editions)
12/30/2016 at 08:06 •
One of the first things that caught my eye, when I did some preliminary research, is the beginning of the Wikipedia page about ECL's history:
Yourke's current switch was a differential amplifier whose input logic levels were different from the output logic levels. "In current mode operation, however, the output signal consists of voltage levels which vary about a reference level different from the input reference level." In Yourke's design, the two logic reference levels differed by 3 volts. Consequently, two complementary versions were used: an NPN version and a PNP version. The NPN output could drive PNP inputs, and vice versa. "The disadvantages are that more different power supply voltages are needed, and both pnp and npn transistors are required."
Can you hear my headgears spinning ?
The provided schematic was actually very tempting:
I'm still confused about the reference things but this got me thinking.
Unfortunately, the link to the original paper is down and I can't get the PDF.
E. J. Rymaszewski; et al. (1981). "Semiconductor Logic Technology in IBM" (PDF). IBM Journal of Research and Development. 25 (5): 607–608. doi:10.1147/rd.255.0603. ISSN 0018-8646. Retrieved August 27, 2007.
But there is a very good reason to use this alternating method : save on the output/buffer/emitter follower transistor (when the fanout is 1 or 2).
For the Germanium version, I only have PNP types. NPN are too rare and out of price for this idea so I'll stick to the classic version.
But I'm planning a Silicon version and guess what ? PNP and NPN are about the same price !
The complementary ECL idea is why I got a bunch of BC549C and BC559C : not as fast and shiny as the AF240 but dirt cheap and flexible. Rated at 250MHz "only", they have a much better amplification that compensates and makes them more efficient as general-purpose switchers. They would probably consume less current (save power) and require less buffers.
Now there is a little problem : for the alternance to work, there must be an even number of "stages" to pass through. Fortunately,
- the "buffer" can be used to skip an alternance
- there are circuits that naturally fit !
One good example of 2) is the DFF gate as described at http://www.play-hookey.com/digital/alt_flip_flops/d_nor_flip-flop.html
(thanks to @Ted Yapo for the link at https://hackaday.io/project/11677-the-diode-clock/log/37976-ddl01-hex-nor-gate )
Do you see those red and blue lines ? Well they can be reorganised a bit but everything is here !
The blue lines can come from NPN gates and the red lines from PNP gates. With one exception (the clock), all the gates go to a complementary gate (PNP to NPN and vice versa). The clock case can be solved by a differential clock signal.
So a one-bit synchronous memory can be designed with 3 PNP gates and 3 NPN gates, each with 3 (or 4) transistors.
I don't think it's a coincidence since I have vague memories about this circuit that I saw long ago and was coming from IBM. The same company that created ECL's ideas...
I write all this here because I haven't yet created a project page for the silicon processor but that's something I'll definitely experiment with !
If the prospect of a 250MHz "only" transistor is worrying, worry not : there are faster transistors (but they are more expensive) and the KSP10 is rated at 650MHz. This will be a welcome speedup for the critical datapath (the adder). And if it's still not enough, the BFR96 is rated at more than 3GHz. Damn, my DDS can only reach 200MHz, I guess I'll have to create oscillators with these very same UHF transistors...
Still there is the old problem of feeding this speed demon with data and my fastest SRAM chips reach only 250MHz (the speed of the Cray-2).
12/26/2016 at 21:02 •
The question of soldering the pins raises the issue of thermal damage, so I looked at the fabrication of the "mesa" type of transistor. I have found quite a lot of informations (thank you Google) but nothing beat "looking by oneself". So I opened on transistor and struggled to make a suitable picture, without dedicated tools...
The wires are really thin ! And they meet at almost the same place, it's hard to distinguish even with optical help...
There are 2 wires, connected to 2 pins. I believe that other than mechanical stress, it's fine during soldering. The wires are straight and can break but the heat might not travel enough through it.
The other two pins are a different story. The "can" pin (who can tell me where to solder it ???) can take the heat but shoudn't get too hot, for many reasons.
The fragile part is the collector (?) : it's the slice of germanium that is directly bound to a pin, and that might propagate the heat to the whole semiconductor. This is the pin to protect with a thermal clamp while soldering...
I broke a few parts but this analysis should help me avoid damage during assembly.
And i still don't know what should be connected to the "package" pin...
12/21/2016 at 19:56 •
Is there anything to be careful about, when dealing with Ge transistors ?
According to a retired engineer, soldering is tricky. I know Ge is very temperature-sensitive but he advised to not cut the leads. I'm still not sure about the exact meaning but Ge transistors can easily get destroyed during soldering. The soldering iron should be set to the lowest possible temperature, and I will find a way to cool the part down before and immediately after the joint is made...
Who else can share their precious advices ?
Now I get it why transistors were socketed back in the days...
And this might be a solution. High frequency signals require short leads and the transistors should barely sit above the PCB plane to keep lengths and traces as short as possible. I'll have to find thousands of individual female sockets that I solder in the PCB holes. I have a "small" stock, maybe a thousand of them, but that is far from enough for a whole system...
(picture found on eBay)
I use these a lot to make prototypes, they are very handy. Unfortunately, all I can find (yet) is small sockets assembled in one (or two) row with 2.54mm spacing. Any hint for where to find individual pins ?
Furthermore, I would cut the smaller end because the larger socket part would go through the PCB. That's a lot to cut...
I have about 4K receptacles of this kind:
First problem : I only have 4K. The AF240 has 4 pins so that's only enough for 1K transistors (barely enough for the register set alone). I got at least 8K AF240 (see below to see how it looks like) so I'd need a crazy 32K receptacles!
Second problem : To get enough receptacles, I'd have to spend about $200 (that's chinese dollars, you know, you get what you pay for...)
Third problem : Reliability. The transistor doesn't move much but... multiplied by 8K, it's a recipe for catastrophe ! I should rather make small modules with a dozen of transistors and test them well (eventually replace a failed part).
Using receptacles, a vibration, a mishandling or any physical influence could perturbate the circuit, making it hard to use. I'd rather damage a few transistors before use, than spend all my time guessing with can got slightly upset...
Concerning soldering : I did some research of the "mesa" technology and it does not seem to be particularly fragile (compared to others) so I'll make a bet by carefully soldering.