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A project log for FPGA Vision

Open fpga image processing

JLAMJLAM 07/03/2014 at 14:330 Comments

There is a link from computer to FPGA. Now the fun begins.

The current setup uses two ring buffers, one on FPGA and one on computer. Data between the two rings are swapped byte by byte essentially forming one big ring. This interface simplifies the communication as the FPGA is piggy backing off the timing from the computer, but does not allow the FPGA to initiate communication. Might modify this in the future.

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