With the Silvercrest SKWD-A1 inspected and found to be nicely hackable it is reasonable to get enough scales to make it through the first iterations without yet again having to gamble and possibly ending up with a less elegant solution.

Futhermore it's hard to beat the 17 mm of this low profile scale. Buying online also made it possible to select a slightly less obtrusive pattern and colour scheme.

It is worth noting that while designs may vary over time the internal construction should be kept more or less consistent once settled upon. It also seems doubtful that there is a lot more room left for further simplification and price reduction so hopefully it'll just stay as is in the next 1-3 years.

In the previous post it has been found that HX711 enters power down when CLK is high for longer than 60 µs and a high to low transition occuring after power down will trigger a reset.

When used behind an I2C multiplexer, DOUT connected to a third data line and SCK connected to SCL, HX711 will see SCK high for a long time before selection (I2C pull-up), followed by bitbanged SCL waveforms which will be composed of the following sequences:

• SCL high-to-low transition: this triggers HX711 reset, followed by a delay period during which reset is executed and presumably the first sampling + conversion with default settings is performed as part of normal continuous sampling operation with channel A and gain of 128 configured.

[ side note: Completion of the first sampling + conversion is indicated by DOUT high-to-low transition. The datasheet only states, "When output data is not ready for retrieval, digital output pin DOUT is high. Serial clock input PD_SCK should be low. When DOUT goes to low, it indicates data is ready for retrieval." which leads to conclude that this also applies to the first conversion after reset. ]

• 25-27 active-high clock pulses on SCL will read the first conversion result and set up for the next conversion with one's choice of channel and gain values.
• After one or more read operations, the bus will have to revert to I2C operation. HX711 will inevitably see an I2C SCL waveform as the I2C multiplexer is reconfigured to disconnect from HX711. This is however irrelevant when the device is disconnected for more than 100 ms as any errorenous conversion will be completed by then and power down is re-established due to secondary SCL being pulled high.

The protocol co-existence described above is enabled by routing DOUT via a third line so it does not interfere with SDA. If connected to SDA, DOUT could create start conditions and lead to invalid I2C command interpretation and lockup.

If only I2C lines are available, one could generate clock pulses to trigger the DOUT high "no new data" state to follow up with I2C multiplexer de-selection but this would also demand converting DOUT to open drain with a diode or MOSFET.

Connecting it to a MOSFET and effectively inverting the output level will have further implications: as long as DOUT is high, SDA will be pulled low so the I2C bus will be in lockup during conversion and possibly also during HX711 power down (not specified in the datasheet).

Next a bit of hardware will be needed to demonstrate the functionality. Ideally the I2C peripheral could be temporarily deactivated and the pins reconfigured for GPIO. Alternatively SCL could be bridged with another GPIO configured as open drain or push-pull if it is guaranteed that I2C will not be driven in the meantime.