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Saluki Board

Linux capable RISC-V SBC

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The aim is to provide an affordable RISC-V SBC that is Linux capable with a similar form factor to the Beaglebone. The design will likely be developed at first using an FPGA and then using custom silicon if the project succeeds.

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AVR wrote 04/17/2018 at 17:35 point

awesome ! What FPGA? Lattice cause its open? Or do you need Xilinx for performance.

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Michael Welling wrote 04/17/2018 at 20:42 point

Ice40 is not going to cut it so I am thinking Xilinx 7 series to follow suit with Yosys. Maybe Artix but It might still be a squeeze. I want it to be affordable so it might have to run "Linux" instead of Linux.

Got some pointers to look at the Ariane implementation.

https://github.com/pulp-platform/ariane

I think I remember seeing that they have it working on a Virtex 7 board with the core using around 19K LUTs.

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Michael Welling wrote 04/17/2018 at 15:29 point

@Charles Sanders You can get RISC-V silicon in microcontroller form with the FE310. Check out my project called LoFive. Though it doesn't have USB and might not have enough pins.

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Charles Sanders wrote 04/16/2018 at 17:38 point

Google alerts sent me here

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Michael Welling wrote 04/17/2018 at 02:02 point

Hey is this your channel?

https://www.youtube.com/channel/UC92VXSLmwHRgpkFNDtWqqXg

I think I might have inadvertently named this project the same as one of your boards.

Probably should have Googled around a bit first. I can rename the project to avoid confusion.

And there we go ... now it is the Saluki Board

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Charles Sanders wrote 04/17/2018 at 03:56 point

I liked the name tanukiboard, but saluki is good too, considering it is a beaglebone-esque form factor. Yes that is my channel. I was actually considering redesigning my board, as I ran into a few design issues involving the PIC used. I was hoping to find a chip made by a manufacturer with better business practices and a more open architecture. I like mips, but being a microchip product really made it undesirable.

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Charles Sanders wrote 04/17/2018 at 03:57 point

I love your idea of using RISC-V, although it will be quite expensive, but perhaps some silicon rolling will occur hehe

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