06/09/2014 at 19:23 •
I’ve been out of the maker game for a while but it seems that life is affording me some minute amount of time once again to do one of the things I love best – making useless stuff for no good reason but to have fun and just because I can. I’m hopeful in any event.
So, in the spirit of all things hacker, I’m back and hereby announce my latest project: the 1 CUP – A Completely Useless and Pointless 8-bit computer built from the ground up!
Inspired to follow in the footsteps of the greats (i.e. Veronica and other such awesomeness), I’ve been wanting to homebrew one of these together myself for quite some time.
Not wanting to defile such greatness as the venerable 6502 and its ilk with my shoddy, arbitrary and completely ad-hoc system design, I’m going to be building my own CPU (well using an FPGA anyway – take that you uber expensive ASIC masks; my business you Certainly Shall Not Have)!
I’m terrible at VHDL but in the interest of Frankensteining something together myself I won’t be Googling that perfect opencore design. Where’s the fun in not screwing it up myself anyway?
During the course of the project you’ll likely observe some truly thoughtless design decisions; I’ll be religiously adhering to the Do It Now, Fix It Later -Maybe directive in the interest of just getting the darn thing done.
The project will include a working, expandable system, kernel, compiler and BASIC interpreter.
So in the interest of kicking off, I’ve done some preliminary CPU work. The CPU is a basic 4 stage FETCH, DECODE, EXECUTE, WRITEBACK finite state machine design with additional FETCH stages for Immediate and Addressing operands. The usual 8-bit data/instruction and 16-bit address buses are present as well. There’s no pipelining damnit!!
Ooo but it *does* boast an MMU which is responsible for mapping in I/O in the form of a bunch of GPIOs, parallel memory bus, and an SPI bus. So it’s a bit of a SoC really.
The plan is to interface with a bunch of expansion boards via SPI; even the display card. It’s probably fast enough for what I need. I seriously want to avoid large parallel buses as I’m hoping to use a TSOP100 packaged FPGA so that I have a hope in hell of soldering it. For the input and timers I’ll probably go with the GPIOs as I’ll need to drive interrupts off them. Perhaps I’ll have them configured through SPI and just use an interrupt line to signal a read… at this stage it’s all a bit up in the air.
In the current CPU feature lineup we have two general purpose 8-bit registers; R0 and R1, a 16-bit Program Counter and Stack Pointer and a 4-bit Status Register (flags and the such).
The CPU sports 2 reset pins – hard and soft. The hard reset vector sees the CPU execute from a fixed memory location (always $1000). The soft reset vector can be defined at runtime via a writable vector table situated at $0000 (also used for defining interrupt vectors, exception vectors, etc.). We’ll delve further into the MMU in a later post.
The oh-so-dirty code thus far is available on Github. Look at your own risk. The dog doesn’t bite but he’s not pretty either so if you don’t like animals please cross the road.
I’m always open to suggestions but if they’re any good I’ll probably ignore them. I’m trying to maximize the amount of blundering after all.