It's indeed reminiscent of Motorola
MC14500 1-bit computers but with no special-purpose chip. All the intelligence is in the EPROM. I admire the ingenuity of this design !
What caught my eyes though is the output register : "4099 addressable latch" that gets 3 address bits, a latch enable and a data input.
Isn't this what I complained that I couldn't find in integrated circuits ?
I have been repeatedly suggested to make a TTL/CMOS version of AMBAP/YGREC but the big roadblock is the register set : all the registers I know are 8 bits with common clock (274, 573, 574 etc.) so a pure bitslice implementation is hard.
Finding a 1-bit wide 8-addresses SRAM chip changes everything and the 4099 maps directly to the address decoder and latches of the register set. Add a few MUX and you're done.
The 4099 however is a bit of an old relic. A lookup on Wikipedia finds however the 74259 : "8-bit addressable latch"
Right : a latch, not a FF/register, just like YGREC is intended to be: a buffer latches the result during a previous clock phase to prevent a direct feedback.
The clear input is welcome but not required. It's precious however for applications as IO port extender, which I'll also consider.
So I just ordered a bunch of these chips and a CMOS YGREC is lurking on the horizon...
Thanks BigEd !
I got convinced into creating #YGRECmos :-)
See the rest there !