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A project log for AMBAP: A Modest Bitslice Architecture Proposal

Trying to unify and simplify a minimal architecture for various implementation technologies...

Yann Guidon / YGDESYann Guidon / YGDES 05/28/2017 at 23:202 Comments

Today, I followed @BigEd's link to his forum where he describes minimalistic systems with one page.

There, I find a description of Dr Jefyll's One Bit ComputerOne Bit Computer

It's indeed reminiscent of Motorola

MC14500 1-bit computers but with no special-purpose chip. All the intelligence is in the EPROM. I admire the ingenuity of this design !

What caught my eyes though is the output register : "4099 addressable latch" that gets 3 address bits, a latch enable and a data input.

Wait.

Isn't this what I complained that I couldn't find in integrated circuits ?

I have been repeatedly suggested to make a TTL/CMOS version of AMBAP/YGREC but the big roadblock is the register set : all the registers I know are 8 bits with common clock (274, 573, 574 etc.) so a pure bitslice implementation is hard.

Finding a 1-bit wide 8-addresses SRAM chip changes everything and the 4099 maps directly to the address decoder and latches of the register set. Add a few MUX and you're done.

The 4099 however is a bit of an old relic. A lookup on Wikipedia finds however the 74259 : "8-bit addressable latch"

Right : a latch, not a FF/register, just like YGREC is intended to be: a buffer latches the result during a previous clock phase to prevent a direct feedback.

The clear input is welcome but not required. It's precious however for applications as IO port extender, which I'll also consider.

So I just ordered a bunch of these chips and a CMOS YGREC is lurking on the horizon...

Thanks BigEd !


20170510:

I got convinced into creating #YGRECmos :-)

See the rest there !

Discussions

Ed S wrote 05/29/2017 at 07:11 point

So glad to have been able to help! I will let Jeff know too.

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Yann Guidon / YGDES wrote 05/29/2017 at 07:24 point

Thank you :-)

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