OnchipWe went all the way to Hsinchu at Taiwan and visit couple of fabs and meet with senior directors to discuss the ins and outs of the project. After going to different details and receiving feedback, we agreed, in most cases, that fabs-lawyer departments have to check details to do something similar to what has been proposed.
The most difficult part is related to NDA "aggregation". Although MOSIS and Europractice (EP), have something similar, MOSIS and EP customers are big schools and companies with a lawyer office backing them which give confidence to fabs. Let's put a case. Let's assume 16 makers decide to do their own digital chip and each of them pay U$350 to get a chip. Each maker require to sign an NDA with the fab to get access, even, to a minimum info such as digital library files containing fab info. Getting a NDA signed with UMC, TSMC, Powerchip or similar fabs require to fulfill some conditions from the maker side.
Although we have had already studied the NDA issue among the outs before visiting fabs, our proposals to solve this issue require full revision from the legal department of the fabs. Brainstorming at the fabs, we believe we have a way to go for the case of digital blocks with a more relaxed NDA. For the analog and mixed signal blocks, there is definitively a longer path and we have to work further details.
We are looking and putting details together to get a detailed plan to go ahead and start our fist prototype with 16 participants. Considering that we will publish soon a call for participation, we would love to hear from interested people the following: what digital chip you would do with a 350umx350um area in 180nm technology 9-tracks standard cells library using qflow ? Remember that you will have access to supply pins, SPI port, JTAG port and regulators besides the area given. Please leave us a comment with the description of the circuit and give us some insights of your expertise to show us that you can accomplish a successful run.
Apart from technicalities, we were amazed that competitors are all across the street:
Since the technology war is quite hot, security measures are obviously enforced. We were not able to take a picture even from the parking lot considering security reasons. Even our laptop got cool stickers:
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If non-digital is possible, then I'd like to try a zero-change silicon photonics chip (no change whatsoever to the process). If not, then an asynchronous ALU.
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I would like to make a Digital Quantum Computer. Currently undergoing construction of a simulator. Even if its a small chip, I am betting it beats the pants off anything we know today. https://hellosemi.com/hypercube/pmwiki.php?n=Main.DigitalQuantumComputer
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We would love to hear details.
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The above link we give gets updated as progress is made. Also, Twitter, https://twitter.com/HelloHypercube we update daily (with many things). The critical moment is when we switch on the hardware simulator which aims to beat an Intel 5GHz. We know software simulations indicates it will thunder past it. But tied to real hardware it should perform miracles and generate great numbers. The only way in at this moment in time is for a big company to put on table serious cash (millions) for a head start over others to develop the range of chips that are mentioned at the web site, but need approval of China investors to agree to the terms. The alternative is to wait until 5GHz Intel chip is beaten to review the implementation details and then decide what kind of opportunities exist.
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"what digital chip you would do with a 350umx350um area in 180nm technology 9-tracks standard cells library using qflow" - for a first product I would synthesize simple CPU that is already proven to work on FPGA. In the minimal case - soviet i8080 without any changes with some integrated peripherals. : https://zeptobars.com/en/read/KR580VM80A-intel-i8080-verilog-reverse-engineering
Too sad that 350x350 fits only ~2KiB of SRAM, so it should have ether have limited onboard ram or rely on external ram chip like original design. The limiting factor could be number of IO pins. i8080 would require at least 35.
I am author at http://zeptobars.com and participated in reverse engineering of this chip so it would be interesting to see how fast can it run :-)
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Hi Mikhail. First of all, great chip pic gallery at zeptobars.com. We love silicon pics.
We like the idea of synthesizing and i8080 Russian version. The number of pins of ihe i8080 are mostly address and data bus pins to connect a parallel memory. Although it might not be a full representation, you might use an I2C-based memory. Remember we provide I2C on the shared area.
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@CloudV, we are integrating opensource digital PnR tools (including those of QFlow) plus others. We went far with this, and we are almost there.
Once released, everyone can design digital IPs and Chips (from RTL to GDSII). Fabrication is a huge issue that we are trying to sort out. Your effort is highly appreciated and will benefit everyone. Validating the CloudV digital flow through a testchip is a must do. We think, a risc-v micontroller which is designed using CloudV could be a candidate for your planed chip.
FYI, we are working on open source RISC-V SoC Editor and HW/SW co-verification toolset to be available through CloudV platform soon.
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I guess you might be Tim or Mohamed. We would love to do a full test of your cloudv flow using our own libs and our shared platform. Please let us know details to make this happen.
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