A completely parallel FPGA ODE solver runs at 25 MSamples/second using Euler integrators. The solver is controlled by the Cyclone5 HPS (dual ARM9). Even a small, two integrator, second order, solver beats the ARM by a factor of 2 in execution time. Bigger models run proportionally faster. The custom floating point is designed to use the DSP units efficiently. Adders and integrators consume about 500 ALM. Multipliers are much smaller. On the DE1-SoC you can fit about 50 operational units. The HPS sets up parameters, then formats and plots the results.
This project is changing. The best source of details is my web page at: